What could we make if the IC took the whole wafer?
The following info is taken from various recent threads...
The P2 (original 16 cogs, 512KB Hub and 64 SmartPins) logic+memories area is looking to be 72 mm2.
We only have 58 mm2 of space in the middle of our huge 8.5 x 8.5 mm die.
The wafer size is 8" (200mm) dia.
350x P2 die fit, but 75% yield gives 262 usable P2's.
A P2 die is 8.5mm x 8.5mm = 72.25mm2
The outer ring frame (Analog+Digital I/O) = 72.25mm2 - 58mm2 = ~14mm2
The synthesis guy just came back and said that the logic+memories area is looking to be 72 mm2.
We have 16 instances of 8192x32 SP RAM at 1.57mm2 = ~25mm2.
... That also halves the main RAM, for now, but I believe they have a 16kx32 instance we could use to keep the hub RAM at 512KB.
We have 32 instances of 512x32 DP RAM at 0.292mm2 = ~9.3mm2.
Those RAMs total to ~34mm2.
Each smart pin is 1/9th the logic of a cog, so 64 of them are equivalent to 64/9 = 7 cogs.
The CORDIC is equivalent to 2 cogs.
So, we have 16 + 7 + 2 = 25 cogs' equivalent of logic here.
This means a cog's worth of logic is about 1.5 mm2 (38 / 25).
So lets play with some numbers...
P2 (16 cog, CORDIC, 512KB HUB RAM, 64 SmartPins, without ring frame) = 72mm2
Plus 512KB SP HUB RAM (1MB Total) = 72mm2 + 25mm2 = 97mm2
Less 64 SmartPins (~7cogs =7*1.5mm2=10.5mm2): 97-10.5 = ~86.5mm2
Therefore, a P2 with 16* 4KB DP RAM COGs, 1MB SP HUB RAM, CORDIC without SmartPins and without the ring frame = ~86.5mm2
A wafer can fit 350 x 8.5mm x 8.5mm = 350 x 72.5mm2 = 25,287mm2 usable per wafer
25,287mm2 / 86.5mm2 = 292 new P2s x 75% yield = 219 usable new P2s.
So lets presume we get 200 usable new P2's(16* 4KB DP RAM COGs, 1MB SP HUB RAM, CORDIC, no SmartPins/IO/ring-fram)
Plus 4 * P2's (16* 4KB DP RAM COGs, 1MB SP HUB RAM, CORDIC, plus 32* Smart I/O Pins and the ring frame for 32 I/O) placed around four sides/edges of the (round) 8" wafer.
Use larger pin pads for easy soldering.
So what do we get...
An 8" (200mm) dia IC with...
I/O: 128 Smart I/O Pins with 64 x 32-bit cores with CORDIC and 4KB DP Private RAM and 4MB shared SP HUB RAM
CPU: 3,200 x 32-bit cores with CORDIC and 4KB DP Private RAM and 200MB shared SP HUB RAM (~4,600 cores if 100% work)
At 200MHz, 2 clock average instructions = 320,000 MIPs plus CORDIC.
And yes, we will require some form of interconnect between these new P2 Blocks.