LOGIC TOO BIG!!!!

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  • cgracey wrote: »
    So, the power came back at 1.5W, typical case, with everything running.

    That's 833mA at 1.8V.
    Excellent news Chip!
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • potatoheadpotatohead Posts: 8,980
    edited October 4 Vote Up0Vote Down
    So, the power came back at 1.5W, typical case, with everything running.

    YES!! Good job Chip!

    All those thoughts about power after "hot edition" paid off very nicely.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • cgracey wrote: »
    So, the power came back at 1.5W, typical case, with everything running.

    That's 833mA at 1.8V.

    Very cool. The power supply won't be a great challenge, and running P2 modules from USB looks like a go! That's going to be fabulous for a "Quickstart 2" sort of concept demo board.

    Surprised and happy!

  • Hi All;

    At 1.5 watts, I believe the chip will be running hot enough to discolor the circuit board unless cooling is provided. My uncalculated expectation is over 100 C package temperature without cooling. On a circuit board, 1.5 watts is a lot. Just run a resistor at that power and see the damage. A passive heat sink will help tons of course.

    So, some concerns here on my part as that power is way more than I had expected. Still waiting with eager anticipation for the real silicon though!

    Cheers,
    Peter (pjv)
  • Fair point Peter, although I was thinking that with such a large ground pad and multiple vdd's, there is potential for plenty of copper to help dissipate that sort of heat.

    Speculation aside; proof will be in the pudding, as you say.
  • potatoheadpotatohead Posts: 8,980
    edited October 4 Vote Up0Vote Down
    And that's 1.5 running balls out. Typical use cases are likely to fall below that power level. Looks like we can have some, "what can you do on 250ma?" competitions to yield efficient code.

    Contest rules:

    P2, any board, running whatever you want connected to current limited bench supply. If it crashes, it's out. GO!

    :D
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • Right, it's unlikely many apps would burn that much power.
  • cgraceycgracey Posts: 8,414
    edited October 4 Vote Up0Vote Down
    The synthesis run that was done yesterday used the original 8192 x 32 RAMs, which resulted in only 256KB of hub RAM. I plugged in the bigger 16384 x 32 RAMs to get our now-8-cog chip back up to 512KB, and they ran the synthesis again this morning.

    The total cell area requirement increased to 7.7 x 7.7mm. I was worried it might exceed our available area, so I measured the GDSII data and, lo and behold, our open space is ~7.70 x ~7.70 mm. That's a luckily perfect landing! That much space is required to keep initial utilization density at 65%, so that by the time the clock tree, the scan chain, and everything else is added, it pretty much fills up near 100%. In fact, any empty spaces will be randomly fitted with unused logic gates of different types, so that minor logic changes can later be realized with only metal masks. That is just for an emergency, of course.

    And the Fmax is ~20% over the 160MHz target, allowing for inevitable reductions due to scan chain, routing extremes, etc. This all means that we should fit okay and hit the 160MHz worst-case-conditions goal.

    Everything is right where it should be, at this point.
  • Instance count, or the number of standard cells, is ~750k. That's 50% more than Prop2-Hot!
  • cgracey wrote: »
    So, the power came back at 1.5W, typical case, with everything running.

    That's 833mA at 1.8V.

    What toggle rate did they assume? Knowing that be useful for those concerned.
  • KeithE wrote: »
    cgracey wrote: »
    So, the power came back at 1.5W, typical case, with everything running.

    That's 833mA at 1.8V.

    What toggle rate did they assume? Knowing that be useful for those concerned.

    I'm pretty sure it was 20%.
  • RaymanRayman Posts: 8,365
    edited October 4 Vote Up0Vote Down
    What was P2-Hot's power draw? Wasn't it 2.0 W?
    Been a while...

    Good thing there is pretty good multitasking implemented with only 8 cores.
    I have to look up if multitasking works with hubexec... Should be fine if it does...

    A little bit of extra RAM, 32k or so would help a lot...
    Prop Info and Apps: http://www.rayslogic.com/
  • P2-Hot was up around 8W.

    XBYTE only runs in cog/LUT RAM. You can make a multitasker from discrete instructions and run code in hubexec, no problem.

    Why do you need another 32k of RAM, and where would you want it?
  • Dave HeinDave Hein Posts: 5,309
    edited October 4 Vote Up0Vote Down
    Rayman wrote: »
    What was P2-Hot's power draw? Wasn't it 2.0 W?
    Been a while...
    It was 3.5 years ago, and P2-Hot was 5W.
    We're looking at 5 Watts in a BGA!
    The P2-Cool is looking great in comparison.
  • Does the P2 have an internal thermometer? If not is it feasible to cram one in? I suspect not because that sounds like the kind of thing that requires another chemical layer.
  • There was some video mode I liked that took almost all 512k...

    1080p at 2 bpp or something
    Prop Info and Apps: http://www.rayslogic.com/
  • This is great news today, Chip! Thanks for keeping us updated.
    I'm sure there's a lot more like me on here that have been following along but rarely post to the P2 forum because a lot of the design grunt work goes over my head. But, we're out here, ready to purchase the final product when it arrives, and happy for your progress. :)
  • Thanks for popping up, DrPop!
  • Hey Rayman, maybe push the code in while the beam isn't looking, run it, and have the streamer follow it with pixels!

    The display only needs that RAM some of the time.

    (I'm kidding)

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 21,412
    edited October 4 Vote Up0Vote Down
    I remember using the Scenix/Ubicom SX18 in a project for a customer. With a 5V Vdd and running at 75 MHz, it got hot enough to require a heatsink, which I adhered to the top of the DIP using JB Weld. According to the SX20 (same chip, different package) datasheet it was dissipating about 0.5W.

    This suggests to me that the P2, at 1.5W, might also need a heatsink if running full-out. The Vss pad on the bottom of the package could be connected to a ground plane on the bottom of the board using multiple vias to conduct the heat. But that creates additional challenges for routing and bypassing the two power busses -- at least on a two-layer board.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • pjv wrote: »
    Hi All;

    At 1.5 watts, I believe the chip will be running hot enough to discolor the circuit board unless cooling is provided. My uncalculated expectation is over 100 C package temperature without cooling. On a circuit board, 1.5 watts is a lot. Just run a resistor at that power and see the damage. A passive heat sink will help tons of course.

    So, some concerns here on my part as that power is way more than I had expected. Still waiting with eager anticipation for the real silicon though!

    Cheers,
    Peter (pjv)

    Junction-to-Ambient for that package is 20C/watt with 0 forced cooling, so you're looking at a 30C rise, if you follow their recommendations for the package. Thats pretty comfortable really.

    Standard packages are more like 40C/watt, 60C rise.

    Looking good...
  • Yep, the Prop2 packaging includes a bottom-side heatsink. The trick will be to spread that in the PCB design. Those doing two layers PCBs will need some extra testing me thinks.

    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • 1.5W is absolute worst case!

    All cogs would need to run hubexec to keep all Hub RAMs active on every clock. CORDIC filled, all 8 streamers running, etc, etc.

    IMHO most of us will be flat out trying to get to 0.5W :)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Cluso99 wrote:
    1.5W is absolute worst case! ... IMHO most of us will be flat out trying to get to 0.5W

    True enough, at least for computing an app's power supply requirements. But for someone designing a general-purpose PCB, methinks it would be prudent to consider the worst case.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • I apologize in advance if this is a stupid question: chip synthesis is not my area of expertise, but how large are the fuses?
    The last I had heard they still had a 1 in 400 failure rate, would it be feasible to drop the fuses as apposed to reduce the total number of COGs?
    I personally can think of a lot more uses for having more cores than fuses that may not work.
  • I must say that 1.5W is pretty acceptable for a package with an internal heatsink pad. If you provide a good layout on your PCB, it will be dissipated. A heatsink glued on to the top would be a plus. I don't expect the PCB to be discolored if there are vias beneath the central pad.

    I write this form experience, since I've designed a board based on the TPS56528 DC-DC converter. At 4A the dissipated power was about 1.7W, on a tiny SO-8 with thermal pad. I had to design a four layer board, but it held, along with other chips also dissipating power to that board. No heatsinks, and no discoloration.
  • The fuses themselves won't be all that big but that area is out of bounds so to speak. If the fuses were removed then there would just be an unused empty space left behind. The whole pad-ring area is finished as a custom analogue layout. It is unlikely to be modified in any significant way. Maybe a component value change.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
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