Prop2 Costs

It looks like it's going to cost $250k to get all the NRE, test development, and mask set done. Then, we can order as many Prop2's as we want.

The process will return prototypes in 23 weeks. That's 5.5 months. Then 12 more weeks to production parts.

Out unit cost will be $5.00/unit, dropping to $4.00/unit when we reach 1M pieces.
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  • Time for the deep breath ? :)
    Those numbers do not sound too bad ?
    Is that cost with them testing the packaged devices, or is that the ready-to-package but not fully tested silicon ?
  • cgracey wrote: »
    It looks like it's going to cost $250k to get all the NRE, test development, and mask set done. Then, we can order as many Prop2's as we want.

    The process will return prototypes in 23 weeks. That's 5.5 months. Then 12 more weeks to production parts.

    Out unit cost will be $5.00/unit, dropping to $4.00/unit when we reach 1M pieces.
    How much would you have to charge for each chip to make money if they cost you $5/chip?

  • So, if you started the process right now, we'd have prototypes in Spring 2018 (March/April), and production in Summer 2018 (July/August). Assuming everything went smoothly.

    Seems like an okay amount of time to get the software ready. We ought to be able to have OpenSpin2 (or whatever we call it) reasonably stable by March for the prototypes. The C/C++ efforts ought to be reasonably good by then too.


  • cgraceycgracey Posts: 8,037
    edited September 29 Vote Up0Vote Down
    jmg wrote: »
    Time for the deep breath ? :)
    Those numbers do not sound too bad ?
    Is that cost with them testing the packaged devices, or is that the ready-to-package but not fully tested silicon ?

    That's for finished parts, packaged and tested.

    I think this looks okay.

    Our die is 8.5mm x 8.5mm, so only 350 untested die fit per 8" wafer. With 75% yield, that's 262 dies. $5 x 262 is $1310. I estimate package and test to be $1 per part, so that means they're charging us $1048 per wafer, which is quite decent, out the gate. Then, those costs drop by 20% by the time we reach 1M units.
  • cgracey wrote: »
    It looks like it's going to cost $250k to get all the NRE, test development, and mask set done..
    Is that using some 'cheapest/simplest' OTP block for Boot ROM and Fuses, as was discussed ?
    If it is OTP, that allows late revisions on Boot, and also allows calibration values & Serial numbers to be put into each device.


  • Roy Eltham wrote: »
    So, if you started the process right now, we'd have prototypes in Spring 2018 (March/April), and production in Summer 2018 (July/August). Assuming everything went smoothly.

    Seems like an okay amount of time to get the software ready. We ought to be able to have OpenSpin2 (or whatever we call it) reasonably stable by March for the prototypes. The C/C++ efforts ought to be reasonably good by then too.
    I believe it would be somewhat later than 'right now' for start, as the PAD ring test chip still needs to be verified and confirmed.
    Some of the early synthesis might run in parallel, but final merge go-ahead would need a confirm the PAD Ring is actually 100% ok.

  • I thought it was EEPROM replacing the fuses and the physical fuses being ignored. OTP wasn't listed at all I didn't think.
  • At the moment, our fuses are in there, still, but they need elevated VIO voltages to blow.

    Frankly, my plate is overflowing with what I've already got on it. I don't want to add more by trying to incorporate that EE block that will need new hookups and firmware to go with it. I'm just DONE making changes. If anything, I may pull the existing fuses out. I want something that I can be very sure about and simulate without caveats. This makes the chip more reliable, but it will have no code protection.
  • Excellent.
  • cgracey wrote: »
    At the moment, our fuses are in there, still, but they need elevated VIO voltages to blow.

    The exact blow curves can be confirmed with the PAD ring chips, correct ?
    cgracey wrote: »
    Frankly, my plate is overflowing with what I've already got on it. I don't want to add more by trying to incorporate that EE block that will need new hookups and firmware to go with it. I'm just DONE making changes..

    Understood, but you really should talk with OnSemi about just what exactly is needed to include EE Blocks, it may not be as scary as you imagine.
    - they are sure to do these all the time, and even an EE Block that is programmed on the tester, makes the device a LOT more sale-able.

    The big marketable gains I see from a programmable memory (be it OTP or EE) are
    * Late BOOT changes are possible, and you can sell special ROM versions to larger customers
    * Calibrate values for measured MHz/KHz of Oscs
    * Serial Number

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 21,240
    edited September 29 Vote Up0Vote Down
    cgracey wrote:
    Out unit cost will be $5.00/unit, dropping to $4.00/unit when we reach 1M pieces.
    As a rough predictor of future sales, how long did it take to reach 1M units of the P1?

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • cgracey wrote:
    Out unit cost will be $5.00/unit, dropping to $4.00/unit when we reach 1M pieces.
    How long did it take to reach 1M units of the P1?

    -Phil

    I don't know. I'm waiting to hear from Ken on that.
  • Is there any possibility of filling the unusable space with a smaller P2 (less hub, less cogs, less smart pins, less pins) ???
    I am thinking of maybe a 4.5x4.5mm or smaller die (maybe 128KB Hub, 8 Cogs, ~32I/O with 16 smart pins) in a QFP/QFN-44/48 or even a DIP40. Or even the die as half and half ?

    I presume the answer is another big synthesis cost and ring frame cost, but since you had previously suggested there could be a family of P2's, maybe this is a possability.

    Might be worth considering/asking ???
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Cluso99 wrote: »
    Is there any possibility of filling the unusable space with a smaller P2 (less hub, less cogs, less smart pins, less pins) ???
    I am thinking of maybe a 4.5x4.5mm or smaller die (maybe 128KB Hub, 8 Cogs, ~32I/O with 16 smart pins) in a QFP/QFN-44/48 or even a DIP40. Or even the die as half and half ?

    I presume the answer is another big synthesis cost and ring frame cost, but since you had previously suggested there could be a family of P2's, maybe this is a possability.

    Might be worth considering/asking ???

    What unusable space are you talking about?

    We could make whatever size part we want. They'd all cost about the same for NRE. First time out, though, we'll make the biggest part possible, with 16 cogs and 512KB hub RAM.
  • cgracey wrote: »
    ... First time out, though, we'll make the biggest part possible, with 16 cogs and 512KB hub RAM.
    Makes sense.
    At what stage do you know how much RAM actually fits ? - that 512k is still a somewhat vague and aspirational 'educated guess'.. ?
    Is the Verilog > 512k ready ? If OnSemi finds more :) (or less :( ) RAM actually fits physically, does that connect-up just fine ?

  • The A9 images have 1MB hub
  • If we can fit more than 512KB, we will. We won't know how much RAM actually fits until they start doing synthesis runs.

    I sent the Verilog files to them tonight, so maybe tomorrow they'll see if it compiles okay.
  • While talking to the foundry/design guys today, it came up that at the really advanced nodes (28nm and below), not much customization is possible, since you kind of have to stick with proven IP. In other words, forget about custom I/O pads. So, for those projects, it's mainly a matter of Verilog handoff. That means if you've got it running on an FPGA, you're ready to go.
  • Heater.Heater. Posts: 19,729
    edited September 29 Vote Up0Vote Down
    cgracey,
    That means if you've got it running on an FPGA, you're ready to go.
    That is an interesting statement. Is it as true as you make out or are their a lot of gotchas in there?

    In another thread around here we were speculating about small outfits getting chips made for cheap, like 100,000 dollars. I argued that if the (logic only) design works in simulation and on FPGA it should ready to go. Others argued there was a ton expensive of work after the FPGA stage I was missing.

    Just idly curious about the possibilities now a days. Might get more serious about it if my lotto numbers were to hit pay dirt.
  • Heater. wrote: »
    cgracey,
    That means if you've got it running on an FPGA, you're ready to go.
    That is an interesting statement. Is it as true as you make out or are their a lot of gotchas in there?

    In another thread around here we were speculating about small outfits getting chips made for cheap, like 100,000 dollars. I argued that if the (logic only) design works in simulation and on FPGA it should ready to go. Others argued there was a ton expensive of work after the FPGA stage I was missing.

    Just idly curious about the possibilities now a days. Might get more serious about it if my lotto numbers were to hit pay dirt.

    Well, there's synthesis and place-and-route NRE expenses that are maybe $100k. Then that 28nm mask set for maybe $1.5M.
  • Cluso99Cluso99 Posts: 12,851
    edited September 29 Vote Up0Vote Down
    cgracey wrote: »
    Cluso99 wrote: »
    Is there any possibility of filling the unusable space with a smaller P2 (less hub, less cogs, less smart pins, less pins) ???
    I am thinking of maybe a 4.5x4.5mm or smaller die (maybe 128KB Hub, 8 Cogs, ~32I/O with 16 smart pins) in a QFP/QFN-44/48 or even a DIP40. Or even the die as half and half ?

    I presume the answer is another big synthesis cost and ring frame cost, but since you had previously suggested there could be a family of P2's, maybe this is a possability.

    Might be worth considering/asking ???

    What unusable space are you talking about?

    We could make whatever size part we want. They'd all cost about the same for NRE. First time out, though, we'll make the biggest part possible, with 16 cogs and 512KB hub RAM.
    The shuttle runs have a lot of different sized dies on the wafer.

    So I was pondering if you could have two sized dies on the one wafer. Provided there was not a big cost and time impact, a small P2 and a large P2 might give you more sales. Obviously the smaller die would be cheaper.

    Perhaps the smaller die might also fit in the spaces that the larger 8.5x8.5mm die will not.

    Probably the mask costs would not increase, or only by a small amount. Not sure if there would be any more synthesis costs.

    It's just like making two different pcbs on a panel. The disadvantage is that whatever mix you decide upon, you can almost guarantee the sales volume will be different. However, you can adjust pricing to try and influence the mix.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Chip,

    Ah yes. 28nm might be pushing the point. But there are companies popping up claiming to be able to get one chips in the 100K ball park. Presumably bigger geometry and ASIC. I wonder how realistic that actually is.
  • Cluso99 wrote: »
    cgracey wrote: »
    Cluso99 wrote: »
    Is there any possibility of filling the unusable space with a smaller P2 (less hub, less cogs, less smart pins, less pins) ???
    I am thinking of maybe a 4.5x4.5mm or smaller die (maybe 128KB Hub, 8 Cogs, ~32I/O with 16 smart pins) in a QFP/QFN-44/48 or even a DIP40. Or even the die as half and half ?

    I presume the answer is another big synthesis cost and ring frame cost, but since you had previously suggested there could be a family of P2's, maybe this is a possability.

    Might be worth considering/asking ???

    What unusable space are you talking about?

    We could make whatever size part we want. They'd all cost about the same for NRE. First time out, though, we'll make the biggest part possible, with 16 cogs and 512KB hub RAM.
    The shuttle runs have a lot of different sized dies on the wafer.

    So I was pondering if you could have two sized dies on the one wafer. Provided there was not a big cost and time impact, a small P2 and a large P2 might give you more sales. Obviously the smaller die would be cheaper.

    Perhaps the smaller die might also fit in the spaces that the larger 8.5x8.5mm die will not.

    Probably the mask costs would not increase, or only by a small amount. Not sure if there would be any more synthesis costs.

    It's just like making two different pcbs on a panel. The disadvantage is that whatever mix you decide upon, you can almost guarantee the sales volume will be different. However, you can adjust pricing to try and influence the mix.

    There'd be an additional $185k for NRE and test development for each different die, even if you could share the reticle set, which I'm quite sure they won't let you do.
  • TubularTubular Posts: 2,827
    edited September 29 Vote Up0Vote Down
    cgracey wrote:
    Out unit cost will be $5.00/unit, dropping to $4.00/unit when we reach 1M pieces.
    As a rough predictor of future sales, how long did it take to reach 1M units of the P1?

    -Phil

    I reckon it was about 2011/12. Can only vaguely recall the announcement. This post of Batang from June 2011 alludes to the announcement

    forums.parallax.com/discussion/comment/1010185/#Comment_1010185


  • Thanks for the update.

    You cannot do anything to reduce NRE cost. And also considering that you have a fixed die size (8.5mm square) and fixed geometry (180nm) you cannot do anything to reduce the unit cost.

    If I were you I would have crippled the design (ram, cogs, instructions, smart pins, ... everything) to make >1000 dies per wafer and get each unit at <$2.50 unit. Less is more, someone said.

    Did you asked about power consumption?

    VAR1: wait / running
    VAR2: 1 cog / 4 cogs / 8 cogs 16 cogs
    VAR3: 32 KHz / 1 MHz/ 16 MHz / 25 MHz / 80 MHz / 100 MHz / 155.52 MHz

    ... (scared) ...
  • Ken GraceyKen Gracey Posts: 6,046
    edited September 29 Vote Up0Vote Down
    cgracey wrote: »
    cgracey wrote:
    Out unit cost will be $5.00/unit, dropping to $4.00/unit when we reach 1M pieces.
    How long did it take to reach 1M units of the P1?

    -Phil

    I don't know. I'm waiting to hear from Ken on that.

    We recently hit a million units on the P1, so it takes a while. Does that recover NRE? Yes.

    P2 will be a different situation, entirely. It would take a poor set of assumptions to somehow calculate that our total investment is somewhat equal to the numbers Chip provided above. They're much larger.

    Ken Gracey

  • I'm puzzled. I thought the P1 hit a million units several years ago. In April 2011 a graph was published that showed a sales growth of about 70% per year. It was also projected that total units sold would probably hit a million by the end of 2011. I hadn't realized that sales had fallen off since then.
  • My guess is that the total cost to Parallax for the P2 will be around $5M. Amortising that over 1M chips would be $5 per chip, meaning a total cost of $10 per P2 chip. Even if Parallax were to minimise their profit per P2, that would be a minimum average sales price of $15 each P2, meaning ~$20 qty 1 to allow for volume users of ~$15 qty 10K. Ouch :(
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • I think qty 1 will be no more than $10.
  • cgracey wrote:
    I think qty 1 will be no more than $10.
    Seriously? That's an awfully slim margin -- especially when you factor in dealer and distributor discounts.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
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