Any other known bugs?

Are there any more known bugs?

I know the smart pins could stand some improvement in the pulse-counting modes, but is anyone aware of anything still broken?

Meanwhile, I will catch up on some threads here that I've not looked at in a while.

Also, we've asked OnSemi to do the synthesis work for us, since it will probably be the least-expensive route for us. We are waiting to hear WHEN they will have some people available to do the job for us.

Comments

  • 8 Comments sorted by Date Added Votes
  • From the standpoint of a hobbyist, the P2 has been perfect for some time:)

    I would eventually like to have a P2 farm.... don't know for sure but I think a cube of 256 P2's would be a good place to start. Anything you could do at no cost and in less than an hour to make this simpler would be appreciated:)
  • jmgjmg Posts: 10,622
    cgracey wrote: »
    Are there any more known bugs?

    I'm not sure USB is working back to full performance/reliability levels yet ?
    cgracey wrote: »
    I know the smart pins could stand some improvement in the pulse-counting modes, but is anyone aware of anything still broken?

    Beside tuning those smart pin modes, I think testing on QuadSPI/OctaFLASH/OctaRAM/HyperFLASH/HyperRAM has been light.

    I think these parts need precise and careful Streamer plus Clock controls.

    It is not clear if these need a DTR pin cell support, for best performance.
    This would take the streamer, at x8 and turn to Quad.DTR near the pin-drive, or take Streamer x16 and turn into Octa.DTR


    HyperRAM is now stocked, but not wonderfully documented around user-refresh, but users do have it working on P1, and I think it can work quite well for display streaming, as most frame times are well inside the refresh limits.

    http://www.macronix.com/en-us/products/NOR-Flash/Pages/OctaFlash.aspx#3V

    Because OctaFLASH can thus also boot the P2, it has natural appeal for those wanting better than QuadSPI performance.


    I also see this from Aug 8th
    http://www.macronix.com/en-us/about/news/Pages/Macronix-Introduces-New-Ultra-High-Performance-OctaFlash-Memory-and-Services-to-Power-Instant-on-Applications.aspx
    Looks like that needs 1.8V ?

    Q: Can the P2 manage mixed 1.8V IO (digital only) now the fuses are not needing 3v3+ ?
    What happens if you power some IO at 1.8V ?

    P2 cannot manage 500MHz, but I was thinking ahead to where it looks like 1.8V may become standard for new memory ?

    OctaRAM is quite new, and very similar to HyperRAM, but I'm assuming is like OctaFLASH which has the SPI fall-back HyperFLASH lacks.

    http://www.jeju-semi.com/Products/OctaRAM
    64Mb A 3.0V 133MHz JSC64SSU8AG 24B BGA 6x8mm JSC64SSU8AGDY-75I Sample Now
  • jmg wrote: »
    Q: Can the P2 manage mixed 1.8V IO (digital only) now the fuses are not needing 3v3+ ?
    What happens if you power some IO at 1.8V ?
    Has to be good for it. They are totally independent rails, both VIO and GIO, for each group of four I/O pins. Each pair should probably be numbered separately. Only the core rails, VDD and GND, are linked all the way around.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • jmgjmg Posts: 10,622
    evanh wrote: »
    jmg wrote: »
    Q: Can the P2 manage mixed 1.8V IO (digital only) now the fuses are not needing 3v3+ ?
    What happens if you power some IO at 1.8V ?
    Has to be good for it. They are totally independent rails, both VIO and GIO, for each group of four I/O pins. Each pair should probably be numbered separately. Only the core rails, VDD and GND, are linked all the way around.
    I'm hoping that's the case, but there are analog cells mixed in all this, and they may have some common bias rails that exclude 1.8V io ?
    I'd expect 1.8V io to also be slightly slower on a 3v3 cell, but I can see cases (more in the future) where 1.8V memory is more 'standard'.

  • cgraceycgracey Posts: 8,321
    edited August 25 Vote Up0Vote Down
    If you run I/O pins at 1.8V, they will barely work in digital mode (300ns response time), and won't work in analog mode.

    You can signal at 1.8V, though, by using digital DAC mode, where you set the high value for the DAC to 255*(1.8/3.3). You can also input 1.8V by using the internal DAC level input set to half the same value.
  • jmgjmg Posts: 10,622
    cgracey wrote: »
    If you run I/O pins at 1.8V, they will barely work in digital mode (300ns response time), and won't work in analog mode.
    Hmm, that's a higher value of 'slightly slower' than I was expecting - that's 4000 CMOS delay territory !
    What is the 3.3V or 3.0V Pin delay ?
    cgracey wrote: »
    You can signal at 1.8V, though, by using digital DAC mode, where you set the high value for the DAC to 255*(1.8/3.3). You can also input 1.8V by using the internal DAC level input set to half the same value.
    What speed and current drain does this have, for 4b and 8b memory uses ?

  • cgraceycgracey Posts: 8,321
    edited August 25 Vote Up0Vote Down
    jmg wrote: »
    cgracey wrote: »
    If you run I/O pins at 1.8V, they will barely work in digital mode (300ns response time), and won't work in analog mode.
    Hmm, that's a higher value of 'slightly slower' than I was expecting - that's 4000 CMOS delay territory !
    What is the 3.3V or 3.0V Pin delay ?
    cgracey wrote: »
    You can signal at 1.8V, though, by using digital DAC mode, where you set the high value for the DAC to 255*(1.8/3.3). You can also input 1.8V by using the internal DAC level input set to half the same value.
    What speed and current drain does this have, for 4b and 8b memory uses ?

    At 3.3V the propagation delays are maybe 2ns, each, for input and output.

    Using 1K-ohm DAC mode as digital output would draw the most current when outputting a high. I think the Idd for each pin outputting 1.8V would be something like 1.7mA. You can multiply that up for 4 or 8 bits. It would be power-hungry, but possible.
  • jmgjmg Posts: 10,622
    cgracey wrote: »

    At 3.3V the propagation delays are maybe 2ns, each, for input and output.

    Using 1K-ohm DAC mode as digital output would draw the most current when outputting a high. I think the Idd for each pin outputting 1.8V would be something like 1.7mA. You can multiply that up for 4 or 8 bits. It would be power-hungry, but possible.
    Ok, that would have to do I guess.
    Fingers crossed the 3V domain has enough customers, to keep 3V products.

    I see this for OctaRAM, so that 133MHz/3.0V is in P2 territory. ( The new 500MHz Octaflash is 1.8V only, but they have 3.0V older ones )

    * Power Supply Voltage: 1.8V / 3.0V
    * Operating Frequency: Max 200MHz (1.8V Device), Max 133MHz (3.0V Device)
    * Single ended clock operation
    * 8-bit multiplexed Command / Address / Data bus (DQ[7:0])
    * Densities: 32Mb, 64Mb, 128Mb
    * Packages: 24-ball BGA
    * DTR (Double-data Transfer Rate) - two data bytes transfer per clock cycle
    * Extended Throughput - up to 400MB/s with DTR operation
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