split from HyperRAM Solutions for P2 (and P1)
The second part or the problem is how to do high speed transfer from P2 into a computer. Mostly I am talking about a PC here, but maybe there are a lot of people right now that would be thinking also in a Rasberry PI, Udoo x86, Odroid, LattePanda, x86duino, Up Board, Olinuxino ... name_your_favorite_SBC_here.
Good question. There are many connection choices, and parallel FIFO is the fastest, but has a somewhat high pin-cost.
I get this table for possible USB Bridge candidates :
EFM8UB1(MCU) CP2102N CP2130 XR21B1420 FT245R FT240X FT232H FT2232H FT4222-C NUC505DLA(MCU) FT600 FT93x
Data Rates 3-4MBd 3-4MBd 3~6MHz SPI ~9MBd 1 MB/s FIFO 1MB/s FIFO 8 MB/s*FIFO 8 MB/s*FIFO 6.725 MB/s HS-USB,QSPI SS,HS USB FIFO HS USB
Price $0.64/1k5 $1.16/1k5 $1.57/1k $2.04/3k $2.65/2k $1.57/3k $2.75/1k5 $3.70/1k $1.530/1k $1.74/1k $6.75/1k $3.65/1k
* Possibly more in SyncFIFO mode
Cheapest Bridge is a small MCU, EFM8UB1 (but this needs software installed, tho SiLabs have drivers+Code)
Cheapest std UART is CP2102N, good for 3~4MBd (4MBd with handshakes)
Fastest FS-USB Uart bridge is the XR21B1420, with fractional baud features and close to theoretical FS speed.
At HS-USB, things thin-out a little, and stalwarts FT232H/FT2232H have parallel FIFO modes for fastest, but many pins cost.
(all HS-USB solutions need a crystal or osc, but precise baud control is not a bad thing to have )
The C rev of FT4222 bumps QuadSPI to 6.725 Mbyte/s, so that starts to look interesting.
The NUC505 MCU is the cheapest HS-USB MCU I can find
, and highly flexible, and can do QuadSPI too.
I'm looking into FT4222H some more, as this seems to be the lowest cost HS-USB standard bridge solution, and the recent improvements lift it closer to the more expensive FT232H/2232H
Longer term, the NUC505 has appeal, (it could do QuadSPI and
Debug..) but for now QuadSPI via FT4222H can test pathways, until QuadSPI via NUC505
The FT4222H has 4 chip selects
, so it could connect directly to the SPI Flash chip, and so allow fast, direct programming.
It can also use another CS,(SS pin32) to slave FT4222 to P2, and so behave very like a COM port.
"The maximum SPI interface operating clock can be set up to 40MHz in master mode and 20MHz in slave mode. With (master) quad mode (4-bits) data bus width, the max data transfer throughput can be up to 53.8Mbps."
Slave mode is 1b only.
SPI Speed choices:
SCK Rate Supported Dividers on Master CLK
1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 SlaveCLK
80MHz 53.8Mbps* 40M* 20M* 10M 5M 2.5M 1.25M 625K 312.5K <= 20MHz
60MHz 39.7Mbps* 30M* 15M 7.5M 3.75M 1.875M 937.5K 468.75K 234.375K <= 15MHz
48MHz 31.5Mbps* 24M* 12M 6M 3M 1.5M 750K 375K 187.5K <= 12MHz
24MHz 15.8Mbps* 12M* 6M 3M 1.5M 750K 375K 187.5K 93.75K <= 6MHz
Some SPI chip selects can be traded off for i2c, or GPIO...
" I2C Master/Slave interface....easy configuration of the I2C as either a master or slave, including target operating speed and bus protocol on the I2C bus.
The device can run at common I2C bus speeds, standard mode (SM), fast mode (FM), Fast mode plus (FM+), and High Speed mode (HS).
A higher bit rate on the I2C bus is also configurable up to 6.66Mbit/s. Clock stretching is supported to conform to v2.1 and v3.0 of the I2C specification"
There are also master/slave choices here..
* Slave Selection when QuadSPI acts as SPI master
– SS0O (pin-17), slave selection to slave device-0
– SS1O (pin-13), slave selection to slave device-1 also is SCL/GPIO0
– SS2O (pin-14), slave selection to slave device-2 also is SDA/GPIO1
– SS3O (pin-15), slave selection to slave device-3 also is GPIO2
* Slave Selection when QuadSPI acts as SPI slave
– SS (pin-32), slave selection for SPI master control. Must tie high when QuadSPI acts as SPI master
Seems Pin17 can connect to SPI.Flash.CS and Pin32 is used when a running P2 wants to talk to FT4222 ?
i2c Speed Choices
SCL Freq = OperatingCLK/(M*(N+1) M=6 or 8 N=1,2,3..127
IF SCL Freq >= 100 KHz, M=6 else M=8
One example : 60MHz, 2.5MHz SCL -> M=6,N=3
Possible P2 connections:
GPIO -> P2Reset Holds P2 in reset, during code download to Flash
QuadSPI <-> SPI Flash device.
i2c <-> 2 P2 Pins
SS <- P2 Pin, for P2 as master link.
QuadSPI -> Flash also connects
MISO (pin-9), data transfer from slave to master for single mode, or data bus bit-1 for dual and quad mode
MOSI (pin-10), data transfer from master to slave for single mode, or data bus bit-0 for dual and quad mode
Link pathway is a one-of choice, PS host can request SPIM (SPI master), or
SPIS (SPI Slave) or
i2c; GPIO seem to have a separate USB interface number in mode0.
So far, this is looking fast and flexible, and low cost. All that is missing is a UART pathway.
Suitable bit packing and unpacking could run 5 SPI bytes as 4 UART bytes.
To avoid RX creep, slave mode may be best, however in this case P2 needs to provide a Baud-clock during the whole TX-RX transaction.
Master mode could avoid 'the P2 provides clock', but creep may be an issue during any long 'P2 replies' phase ?
Possible solution could be a 1GU04, to have P2 clock from the 12MHz Xtal Osc on FT4222 ? (or, a 12MHz OSC module, drives both chips)
Mouser show UMFT4222EV-C Stock: 78 1+ $14.95