I've been spending time speeding up critical paths. One thing that has been sticking out like a sore thumb for a long time is the JP/JNP instruction combo. It takes a long time to mux one of 64 INA/INB pins and then propagate it through the branch logic, in order to gate several late circuits. It's like a tent pole lifting up the amount of time required for the cog to cycle.
I looked all through my code base and I've never even used JP/JNP. Not sure why, but I think I tend to code not so directly as to branch on a pin state.
If I get rid of JP/JNP, things speed up quite well and a lot of resultant paths become very tame. In fact, in asking Quartus to identify bottlenecks, which it rates with priority numbers, things really flatten out when the JP/JNP combo goes away. I mean, the bottlenecks all take on about the same value, which means there was one tent pole tending to hold up everything - JP/JNP.
So, would anyone be upset if I got rid of JP/JNP?
By the way, the next release is looking like no problem for 100MHz.