RISC V ?

1101112131416»

Comments

  • SiFive has made a multicore RISC-V chip. Some infos here

    - 5 cores RISC-V 64 bit
    - 2 MByte chache RAM
    - up to 2.6 GHz clock
    - 28nm process, 30 mm2 die size
    - HiSpeed link to FPGAs

    - no USB on chip
    - no Flash on chip

    Evalboard early next year


    There are also a few other companies that work on multicore RISC-V chips.
    But there is still a long way to go until the industry adopts RISC-V and you can buy
    cheap controllers with RISC-V comparable to all the ARM Cortex M0..M4 controllers or the MIPS based PIC32s.

  • A 28nm process real, physical RISCV is actually interesting. I wonder what the cost of the eval board will be. If it's reasonable I would be interested.
    Downside is that the hypervisor mode is software, not hardware implemented. But I could live with that.
  • Fantastic.

    I suspect those wily Chinese might be on the RISC-V case soon enough. Consider devices like the ESP8266/ESP32. They use Xtensa processor cores from Tensilica. Why license a CPU core when you can just get one for free? RISC-V could make it possible for lots of little guys to get their ideas off the ground with minimal fuss and expense.

    I wonder what that high speed link to FPGA looks like. Perhaps we can hook the P2 it.

    Interestingly the 2M Byte cache can be configured as simple static RAM for real-time determinism. 2M Byte is a good size space. Perhaps the whole thing can run with out any external RAM.

  • Ariba wrote: »
    SiFive has made a multicore RISC-V chip. Some infos here

    - 5 cores RISC-V 64 bit
    - 2 MByte chache RAM
    - up to 2.6 GHz clock
    - 28nm process, 30 mm2 die size
    - HiSpeed link to FPGAs

    - no USB on chip
    - no Flash on chip

    Evalboard early next year

    I see the link says this
    "The system is supported by the Eclipse-based Freedom Studio that runs on Windows, Linux, and MacOS.
    The chip will work with JTAG emulators like Segger’s J-Link Probe."

    That could be significant & useful for P2 debug, if P2 can run a JTAG(subset) interface well enough via smart pins ?
    Can the streamer do 2 bit wide ?

    ...and the FPGA link is called ChipLink, but I suspect may be LVDS - too fast/incompatible with P2.
    However, it does also show QuadSPI, UART, SPI, i2c, GPIO peripherals, so maybe those have enough speed to be useful ?
    Also shows ROM and OTP, but I cannot find how much OTP ?

    At the other end of the scale, I see this $25 PCB for the smaller sibling.
    https://hackaday.com/2017/09/18/a-smaller-cheaper-risc-v-board/
Sign In or Register to comment.