General Planning

2

Comments

  • cgracey wrote: »
    Right now, I'm just trying to get v16 out and it's enough to think about. Then, I want to concentrate on Spin 2. That's all I got.

    Will you just port the current (P1) Spin into P2, or create the new Spin 2?

    I imagine that there are two ways to implement the interpreter:

    a) Port P1 SPIN into P2. 100% compatible, or 99% with minor modifications.
    b) New P2 SPIN 2. Full featured with all new instrucion set of P2.

    Option A should not take so long. It is a single concrete task that doesn't need to invent anything. And we can test if P1 code will run on P2 without major modifications.

    Option B is a recipe for disaster. The new can of worms. Another creative process. I will take 2 or 3 years (5?). (I agree with cluso on this). We will be discussing for ages if this option is better, or if we should do this or that. There is the added risk that might attempt to modify the currently frozen P2 v16 Instruction Set just to accomodate the new great idea designed for SPIN 2.

    You want SPIN. OK. But please, can we agree that at this stage, we just need only in a P1 compatible SPIN first? ... and later, once you have that, you can create the new perfect SPIN2?

    Once both of them are finished they just can be merged in one single SPIN2 with one directive, like [ORG], to indicate the mode [P1] or [P2]
  • Ramon wrote: »
    cgracey wrote: »
    Right now, I'm just trying to get v16 out and it's enough to think about. Then, I want to concentrate on Spin 2. That's all I got.

    Will you just port the current (P1) Spin into P2, or create the new Spin 2?

    I imagine that there are two ways to implement the interpreter:

    a) Port P1 SPIN into P2. 100% compatible, or 99% with minor modifications.
    b) New P2 SPIN 2. Full featured with all new instrucion set of P2.

    Option A should not take so long. It is a single concrete task that doesn't need to invent anything. And we can test if P1 code will run on P2 without major modifications.

    Option B is a recipe for disaster. The new can of worms. Another creative process. I will take 2 or 3 years (5?). (I agree with cluso on this). We will be discussing for ages if this option is better, or if we should do this or that. There is the added risk that might attempt to modify the currently frozen P2 v16 Instruction Set just to accomodate the new great idea designed for SPIN 2.

    You want SPIN. OK. But please, can we agree that at this stage, we just need only in a P1 compatible SPIN first? ... and later, once you have that, you can create the new perfect SPIN2?

    Once both of them are finished they just can be merged in one single SPIN2 with one directive, like [ORG], to indicate the mode [P1] or [P2]

    Spin1 byte codes are limited to 64KB. It needs redoing. This process is not nearly as tedious as Verilog and schematic work.
  • Even if they are limited to 64KB, I still think that it is a good idea try to port P1 spin into P2 first (with that same 64KB limit). Just because we have already a lot of SPIN code we can test. And for the other reason above (we don't need to invent, it is just a more simple task).
  • If I understand it correctly. There is no technical limit to try to port P1 spin into P2. It is just that we are not using the full hub address space. It's just limited to 64Kb instead of using full 256 KB, right?
  • Ramon wrote: »
    If I understand it correctly. There is no technical limit to try to port P1 spin into P2. It is just that we are not using the full hub address space. It's just limited to 64Kb instead of using full 256 KB, right?

    There are lots of details in there that would make it a lot more worthwhile to just redo it. It's really not the big job you are imagining it is. All the elemental pieces are ready to be reused in Spin2.
  • Ramon wrote: »
    I imagine that there are two ways to implement the interpreter:

    a) Port P1 SPIN into P2. 100% compatible, or 99% with minor modifications.
    b) New P2 SPIN 2. Full featured with all new instrucion set of P2.

    ...
    And we can test if P1 code will run on P2 without major modifications.

    This depends on the values of 'minor' and 'without major'.
    There is merit in having a P1-Compatible mode, FreePascal has a number of Compiler modes, for backward compatibility.
    The devil is in the details, and things like WAITPNE and WAITCNT and 2 local Timers, have no exact equivalents in P2, so I doubt 100% or 99% will be possible.

    What could be useful in this space, is a a software tool that is part-simulator, and part configurator.
    It would need to extract what counter mode P1 code was using, and then craft an equivalent, using P2 hardware.

    Not sounding trivial, but it would be useful.

  • Ramon wrote: »
    If I understand it correctly. There is no technical limit to try to port P1 spin into P2. It is just that we are not using the full hub address space. It's just limited to 64Kb instead of using full 256 KB, right?
    P2's counter modes are now handled by the smart pins. You would have to write PASM drivers to configure/use these modes in SPIN1, what a pain.
    No trig/log/font tables, different video blocks and many other little differences,
    IMHO a new SPIN sounds like the way to go.

    Melbourne, Australia
  • There is no possible way to easily port Spin to the P2. Or even make a Spin compatible Spin 2.

    Why? Because Spin includes PASM. The machine architecture has totally changed so that is out.

  • Yup. And that's fine. New hardware, new custom environment tuned for it. What will fall out of that is a lot of stuff that can be used in a more portable way.

    Been thinking about P1. WAITVID is gonna be hard to do. That's out. New video drivers can duplicate the memory schemes, colors, pixel depths, if people want that. It's not a big deal there.

    But, counters? Maybe those can just be done with a counter COG or two. When the real chip is running at speed, emulation of those features may make sense for some code. But then again, so will rewriting it.

    Will be interesting to see what people do.

    I very strongly believe in having an all in one design available. P2+Spin+PASM will make exploiting the hardware, learning about it, and all that accessible. This is needed! It's not hardware that works and looks like most other hardware. And it's intended to bring people close to the signals and close to the silicon. There are advantages to that. They are not portable advantages.

    This actually goes back to the BASIC discussion thread. "Impure" BASIC variants mooched the design ideas that made the basics accessible. Extensions, PEEK, POKE, in-line assembly, callable routines, special keywords all presented the machine in a way that an ordinary person could make sense of. All of that paid off nicely on those machines. Of course, it's dated now, but was always going to be dated at some point. However, if one has those machines, they still do exactly what they did, and where they were useful, they remain so.

    P1 is like that. P2 is going to be like that.

    And that right there is the trade-off. Given it's all available for a considerable time, people can build skills once and then just apply them with few worries. This is worth giving up portability for. Not always, not for all people, but enough that it should exist.

    Finally, think of it this way. Competitive advantage! :D In that recent project I was on, those P1 skills I had learned nailed the basic requirements needed to advance things and put the whole thing into testing the physics and science portion. A more portable, general purpose solution happened to have a lot more overhead, which just got in the way.

    That physics and science, by the way, is proving to make some of the more general, portable solution moot! Bunch 'o code got written that just isn't ever going to be used. Sure was nice to find that out early before the investment got too great.

    Those guys can read the SPIN easily enough. When it's time, and on the next round, plucking out the useful info to be coded in C and on the target device won't be a big deal. Result = portablish! But, getting there on P1, basically funds doing this too. The savings was worth it. So really, it all is a wash, kind of a freebie in that respect.

    I'm always careful not to dismiss the expectation of reuse, standards, and all that. It's totally valid, and we see that play out all over the place. I'm not anti at all. I'm just pro having something raw, wild, accessible, potent too. When used in the right time, place and manner, it's a win, which is why it should exist.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • Have you considered Mixed Core scenarios' ?

    What about 8 cores P1 and 8 cores P2

    Drop SPIN for the P2 and use P1 SPIN

    P2 development only in P2ASM and then later C

    100% Backward compatibility by running SPIN on P1 cores only

    Use P1 to bootstrap P2 cores

    Get on with it..
  • Lol, damn, I gotta stop reading these topics.
    $50,000 buys you a discrediting of a journalist
  • Ken Gracey wrote: »
    OpenSpin must be finished before we have chips
    OpenSpin but not GCC?


  • OK, now we are getting back to having 15 chefs in the kitchen again...

    Having Spin1 compatability would be nice, however I really think that should come after Chip completes Spin2 as he has envisioned it. Objects and methods that are useful will be updated to Spin2 by someone, if they are truely useful.
    Having Chip waste time now on Spin1 compatability when Spin2 is going to be the future, is IMO an inefficient use of his time.

    Talk about mixing Cores is also plain dumb, and leads to my next point.
    I honestly think Ken or Chip might want to consider just nipping a lot of the 'suggestions/schedules' right in the bud.
    The whole Open Design process has been completed for the most part, and the remainder is the grunt work on s/w, testing, errata, etc. Parallax has done this many time before, and know what they are doing.

    I'd like to see folks who start pushing for this or that major h/w or s/w feature to include in concrete terms what resources they are going to provide Parallax directly, as in x hours per week testing, documentation, SW development, $$, etc.

    A milestone has been reached.

    Parallax needs to decide how they want to proceed, and then simply explain that and move forward with THEIR plan and reply with 'Out of scope' for the more outlandish requests.

    Thats my 2-bits worth.
    ---- This space available for rent ----<br>
  • It's been fun watching people who have no idea how the internals work making helpful suggestions to get the chip done. Like mixing P1 and P2 cores in the same chip, as though their architectures are fully compatible, or just porting Spin1, whose architecture is wholly incompatible with P2 in nearly every way, from a 15 year old Delpi code base.

    This thread is borderline ludicrous. From the title, I thought it was Chip or Ken posting a release timeline and thought, "holy crap! Is this thing almost done?" But, sadly no, it's just another impatient rando playing with my emotions.

    If the mods are looking for threads to sink, I have a suggestion.
  • JasonDorie,
    You said it better than I could. Totally agree.
  • marsman2020marsman2020 Posts: 1
    edited February 26 Vote Up0Vote Down
    I've been lurking for a while watching this thing shape up and it seems to me that the best way to make this happen faster is to put in the time to buy an FPGA board and help with testing/feedback.

    Making threads titled 'General Planning' when one is not 'on the ground' at Parallax seems quite presumptuous and really does nothing but confuse people (was super excited when I saw the thread title, until I realized what it really is).


  • JasonDorie wrote:
    If the mods are looking for threads to sink, I have a suggestion.
    +1

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • This thread is going to be sunk, since it was not an official announcement from Parallax.
    Infernal Machine
  • Thanks!
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • +1
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • OMG, +1 here too...
    ---- This space available for rent ----<br>
  • Cannot believe it.
    We compain about thread locking and thread sinking.
    And what do we ask for? (guilty too)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Cluso99 wrote: »
    We compain about thread locking and thread sinking.
    And what do we ask for? (guilty too)

    We complain when it's opaque, decided from on high, with little apparent reason. I'd be surprised if anyone here disagrees that this thread should be locked, sunk, deleted, drawn, quartered and spat upon. And that wasn't my first spelling of "spat".
  • I changed the title of the thread.

    The purpose of this thread was to check the grade of commitment for completion from Parallax itself.

    An attempt to obtain any more detailed information than just the politically-correct and forum-auto-imposed sencence "the P2 will be done when it is ready."

    All you can made your guess about when this project will finish.
  • Publison wrote: »
    This thread is going to be sunk, since it was not an official announcement from Parallax.

    The purpose was just that. Get an official announcement from Parallax.

    And we already got the response:

    Ken: [my on words on] I would like to have schedule/plan on P2, but I have a business to run, that depends on Chip[my on words off]
    Chip: [my on words on] I just focus on what I am going to do next. That's it. [my on words off]

    So this means for me alpha stage. And maybe 3 to 5 years more debating about how SPIN2 should have or not. With SPIN v1 , v2 , v3, v4, v5 ..., v15, and v16 ... until someone who's opinion have enougth weight on this forum say something like "I'am going to join the ARMy". Then suddenly SPIN will be frozen, and we will be able to start with something else.
  • Making threads titled 'General Planning' when one is not 'on the ground' at Parallax seems quite presumptuous and really does nothing but confuse people (was super excited when I saw the thread title, until I realized what it really is).

    I am very sorry to make you feel like that. I didn't wanted anyone to feel that this was an official announcement. I already changed the title.

    We all want the P2 to be born. Now, after reading the thoughs from Parallax, do you feel any better?





  • JasonDorie wrote: »
    This thread is borderline ludicrous. From the title, I thought it was Chip or Ken posting a release timeline and thought, "holy crap! Is this thing almost done?" But, sadly no, it's just another impatient rando playing with my emotions.

    Apologizes to all. I feel very sorry. "The P2 will be done when it is ready" as we are used to read.

  • David Betz wrote: »
    Hmmm.... That's a depressing thought. I'm sure Chip's x86 version of Spin2 will be done in time.

    Yes, it is depressing. Do you have privileged information? What will be the time for Spin2?
    Wait, I shouldn't had asked that question. "SPIN2 will be done when it is ready".
  • Dave Hein wrote: »
    Mike Green wrote: »
    As much as some people might wish, Parallax doesn't work to deadlines. In most businesses, deadlines either produce inferior products or they're ignored. Chip and Ken want to produce quality products that will have a useful lifetime of many years. It'll be done when it's done. If you have a product to build and ship, by all means use some alternative microcontroller. You can use a Prop 2 in your version 2 product.
    Mike, I totally disagree with your statement about deadlines versus quality. Many, if not most businesses do develop schedules with deadlines, and do produce quality products. The notion that you can't produce quality products and have deadlines is ludicrous.
    The truth is somewhere in between, I believe. Deadlines make sense for companies with engineers that don't believe in "perfection is the enemy of good", and therefore keep fiddling with the product, never finishing. But for a lot of other companies deadlines are management- or marketing imposed, with no real reality checking. And then there are companies where deadlines are reasonably well thought out, and the deadlines are used for planning purposes ("when are we going to start purchasing and gearing up for the next product").

  • T ChapT Chap Posts: 3,583
    edited February 27 Vote Up1Vote Down
    Any outside and forced discussion of schedules and deadlines on the P2 can only be consider antagonistic since there is no point trying to assign deadlines. It will be done when it is done. Making comparisons to how other companies do it is only going to be taken as antagonistic, since it is clear Parallax is not doing this as other companies would do it.

    Any thread that is purely here to antagonize should be deleted as it is counter to the community vibe.

    BTW How many sales of your product is Parallax holding up because P2 is not out? Can you even justify 100 units of P2, or even 1000 to be putting such pressure on a company that owes you nothing? Is P2 holding up 10k - 100k units of your product? If so then you should not be in business in the first place and more importantly you should have better things to do that bait the forum with this stuff non productive stuff.

    Whether moderated or not, it should be generally understood what you are getting into if you are interested in the P2.... and posts contrary to "knowing what you are getting into" are only a distraction.
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