P1V - with Lattice ECP5 FPGAs?

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  • Interesting to read about the TinyFPGA EX progress, as haven't checked it out in a while. In some earlier work I did I found that the Lattice ECP5 FPGA family is pretty much an ideal match for a low cost complete P1V implementation with room for some extra peripherals. Specifically the ECP5 LFE5U-25F FPGA variant was a real sweet spot. Pity that part is not one of the targets of the TinyFPGA EX though as Luke seems to have chosen the 12F, 45F, and 85F parts for his board. So you would need to either get the -45F model or above for a full 8 COG P1V and this leaves heaps of spare space, maybe you could even squeeze two bare bones P1Vs in it or a 16 COG variant with some redesign of the hub.
  • jmgjmg Posts: 14,240
    I'll bump this with info on a new FPGA player.

    Of interest here are mention of mask-ROM (Up to T120 parts) and hard-IP in the interface areas. eg DDR3 allows lots of low cost SDRAM to be added.


    https://www.efinixinc.com/docs/trion-overview-v1.7.pdf


    Page 1 prices update and Trion added.
    ECP5-Part           LUTs  $@1   Cogs   RAM  IOs max  MULs
    ----------------------------------------------------------
    LFE5U-12F-6BG256C   12k   6.26    ~6   589kb   ~190    28
    LFE5U-25F-7BG256C   24k   9.29  8..12  1032kb  ~190    28
    LFE5U-45F-7BG256C   44k  15.86   16+   1990kb  ~196    72
    LFE5UM-85F-7BG381C  84k  38.08   16+   3833kb  ~196    156
    
    Trion FPGA          LUTs  $@1   MaskROM    RAM   IOs max  MULs PLL MIPI  LVDS T,R  DDR3,LPDDR3,LPDDR2(800 Mbps)
    --------------------------------------------------------------------------------------------
    T13F256C3           12k  12.56    Y       744kb   ~190    24   5   2T2R  13,13     -
    T20F256C3           19k  18.02    Y      10369b   ~190    36   7   2T2R  20.26     x16
    

  • jmgjmg Posts: 14,240
    .. and more FPGAs, these from lattice
    CrossLink-NX Device Selection Guide
    Features	                                LIFCL-17	LIFCL-40
    Logic Cells	                                17K	        39K
    Embedded Memory (EBR) Bits (Kb)	                432	        1512
    Large Memory (LRAM) Bits (Kb)	                2560	        1024
    18 X 18 Multipliers	                        24	        56
    ADC Blocks	                                2	        2
    GPLL	                                        2	        3
    Hardened 10 Gbps D-PHY Quads	                2	        2
    Hardened 2.5 Gbps D-PHY Data Lanes (total)	8	        8
    5 Gb/s PCIe Gen2 Hard IP	                —	        1
    
    0.4 mm Total I/O (D-PHY, PCIe, Wide Range, High Performance)
    LIFCL-17	                                                LIFCL-40
    72 wlcsp (3.7 x 4.1 mm)	36 (1, 0, 16, 20)	                —
    
    0.5 mm Total I/O (D-PHY, PCIe, Wide Range, High Performance)
                            LIFCL-17	        LIFCL-40
    72 QFN (10 x 10 mm)	40 (1, 0, 18, 22)	40 (1, 0, 18, 22)
    121 csfBGA (6 x 6 mm)	48 (2, 0, 24, 48)	72 (2, 0, 24, 48)
    289 csfBGA (9.5 x 9.5 mm)	—	       180 (2, 1, 106, 74)
    
    0.8 mm Total I/O (D-PHY, PCIe, Wide Range, High Performance)
                            LIFCL-17	        LIFCL-40
    256 caBGA (14 x 14 mm)	72 (2, 0, 24, 48)	152 (2, 1, 78, 74)
    400 caBGA (17 x 17 mm)	—	                192 (2, 1, 118, 74)
    
    fIN Input Clock Frequency (CLKI, CLKFB)          10 — 500 MHz
    fOUT Output Clock Frequency                      6.25 — 800 MHz
    fVCO PLL VCO Frequency                           800 — 1600 MHz
    
    fCLKHF  HFOSC CLKK Clock Frequency              405    ~  450  ~  495   MHz
    fCLKLF  LFOSC CLKK Clock Frequency              121.6  ~  128  ~  134.4 kHz
    

    Price indications are showing for LIFCL-40-7SG72CES IC FPGA Crosslink-nx Es 72QFN ~$31.25
    - nothing showing for LIFCL-17
    The QFN72 is the roughly the same size as P1, and appears to support both parts, which could be flexible. Or, the 6x6mm BGA is very compact.
    Data shows a HFOSC of 450MHz and 28nm process.

    This detail is interesting :
    Instant on performance – to better support applications where a long system boot time is unacceptable, such as industrial motor control, CrossLink-NX enables ultra-fast I/O configuration in 3 ms and total device configuration in less than 15 ms.
    P1V and P2 could be designed to do a similar thing, where IO is defined faster than total boot time. ?
  • Thanks for the update jmg. Looks like they are competing with Max10 (1Msps ADCs, "instant on")

    I had a bit of a look. The device with more LE's gains them at the expense of less memory, unfortunately

    I also found "project trellis" that is making inroads into the configuration bitstream of the ECP5 series, which is exciting

  • AleAle Posts: 2,358
    Nice parts ! and the same package the MachXO3D is getting (QFN72).
    I don't know though when these parts will be available, the MachXO3D showed up like in May this year, today I consulted Mouser agaian and finally they show an availability date... Sept 2020 !... let's see what happens.
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