P1V - with Lattice ECP5 FPGAs?

I just noticed that the price of the Lattice ECP5 devices dropped dramatically on Digikey to lesser than half the price as before.
I'm not sure if it's not a mistake by Digikey because all the other Lattice distributors list still the old prices.I hope Digikey is just faster.

Anyway with this new prices P1V can become competitive to P1 silicon devices:
ECP5-Part  LUTs  $@1   $@100  Cogs   HUBRAM  IOs max  MULs
----------------------------------------------------------
LFE5U-12   12k   6.26  5.25    ~6    52 kB    ~190    28
LFE5U-25   24k  11.51  9.72   8..12  96 kB    ~190    28
LFE5U-45   44k  21.62  18.25   16+   184 kB   ~196    72
LFE5U-85   84k  31.26  27.48   16+   384 kB   ~196    156

They are currently only available in 381 ball BGAs with 17x17mm size and 0.8mm ball pitch. Later there will be also also 10x10mm with 0.5mm pitch variants.

No cheap Evaluation board so far, but when the 10x10mm parts will be available, Valentin from Fleasystems will produce the Flea-Ohm board for 33$, with a lot of useful connectors.

The biggest ECP5 part with 84k LEs may also fit 4..5 P2 cogs with some smart pins for ~30 $ !


Andy
«13

Comments

  • 83 Comments sorted by Date Added Votes
  • Now that's looking really interesting, especially the -25 device that would hold a full prop and more

    Wonder what MHz they would run at.

    Thanks for sharing, Andy
  • The LFE5U-12 costs less than a real P1 chip and has more RAM (but fewer COGs)!
  • Ariba wrote: »
    I just noticed that the price of the Lattice ECP5 devices dropped dramatically on Digikey to lesser than half the price as before.
    I'm not sure if it's not a mistake by Digikey because all the other Lattice distributors list still the old prices.I hope Digikey is just faster.

    Well spotted.
    Those prices do not show yet in the Lattice store, but they are across more than one line-item, and Octopart has a few Future lines that where they do appear, they show (slightly) lower prices than Digikey.
    Unlikely that both Digileyand future make the same typos ...
     Future Electronics 	LFE5U-45F-6BG381I 	1+  $17.82 	
    
  • roglohrogloh Posts: 563
    edited December 2016 Vote Up0Vote Down
    Has anyone had any success so far in porting P1V to run on Lattice FPGAs?
    If so, and that FleaOhm board comes through one day that looks like a really nice match and compatible with Raspi HATs too.
  • Ariba wrote: »
    ....

    No cheap Evaluation board so far, but when the 10x10mm parts will be available, Valentin from Fleasystems will produce the Flea-Ohm board for 33$, with a lot of useful connectors.

    I notice Lattice have a $99 promo on Boards
    http://www.latticesemi.com/ECP5Promo

    Not sure if the Free Diamond can compile for all, as they mention $99 here ?



  • See the list
    2400 x 1020 - 96K
  • Basman74Basman74 Posts: 7
    edited October 3 Vote Up0Vote Down
    Hello Everyone!

    I'm the creator of the FleaFPGA 'Ohm' board mentioned in this thread.

    Permit me to say: Thought it may interest you to know that I have now launched my hobby board as an Indiegogo Campaign. If anyone has any questions about it, feel free to ask. Thanks!

    Regards,
    Valentin Angelovski
  • TubularTubular Posts: 2,837
    edited October 3 Vote Up0Vote Down
    Valentin, welcome

    There's a few of us here in mel who dabble in P1V's (Propeller 1 verilog). We meet up from time to time out east, and fleaohm came up in discussions just a week or so ago, so you have excellent timing. What we're most curious about is how fast a P1V would run in lattice architecture (our experience is mostly Altera Cyclone IV, V, max10 and very soon cyclone 10). Most of the active work around here has been on Altera or Xilinx.

    Will let you know next time we're meeting in case you're interested . And best sign up for your campaign too

    cheers
    Lachlan
  • roglohrogloh Posts: 563
    edited October 4 Vote Up0Vote Down
    Hi Valentin,

    I've followed your work on this project for some time and it looks really impressive. Have always wanted pretty much the same type of board with the same feature set for P1V experimentation as your Flea Ohm design offers. In the past I've done some SDRAM, audio and video expansion work for P1V and your board seems to be almost a perfect fit for experiments in this area however I'm unsure if anyone has had luck with getting P1V Verilog going yet with Lattice FPGAs. No one here has said they've got it ported fully yet (to my knowledge). However if some Lattice tools for this FPGA are freely/cheaply available it would be very tempting to try to get a P1V working on your board once it's available. That would help extend the market for your board too.

    As Lachlan mentioned from time to time we also meet up with OzPropDev locally here in Melbourne, sometimes over a beer or two at a pub, and we are probably due for another soon. If you are interested it could be quite good to meet up and discuss various FPGA projects we've done and I suspect we may share similar interests in the whole retro computing gaming thing too (same age group).

    Cheers,
    Roger.
  • Roger,
    I'd be interested too, providing I can get a cheap fare and my wife's better (just had a double knee replacement). I know Peter would be interested too.
    Ray
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Sure let me know when suits. Tends to be cheaper to fly to Avalon and I can pick you up from there almost as easily
  • Basman74Basman74 Posts: 7
    edited October 4 Vote Up0Vote Down
    Gentlemen,

    Honestly, I had no idea there was a propeller movement in Melbourne! I need to stop inspecting FPGA hardware through a magnifier and get out more..

    I am honored and humbled by your interest in my hardware. You guys have done some amazing embedded projects yourselves and know your stuff. Would definitely be interested to meet up with you guys and talk tech/retro over a beer or two..

    As for the burning question: I noticed the P1V was ported to the Max10 FPGA recently. I firmly believe that if it runs on a Max10, then it should (imho) also run on a Lattice ECP5 series FPGA..

    @ Ray,
    As a carer of a sick spouse myself, I wish your wife a speedy recovery.

    Cheers,
    Valentin
  • Gday Valentin
    Welcome to the forum!
    Looking forward to seeing your FPGA board and catching up with the lads. :)
    Cheers
    Brian
    Melbourne, Australia
  • BTW - for those interested in Lattice...

    First off it seems like the Icestorm support of the iCE40 Ultra parts (by Adafruit employee) has stalled.

    Lattice was almost purchased by Canyon Bridge, but it looks like it was blocked.

    https://www.bloomberg.com/news/articles/2017-09-13/trump-blocks-china-backed-bid-for-chipmaker-over-security-risk

    Meanwhile Canyon Bridge bought Imagination, with MIPs going to Tallwood:

    https://www.bloomberg.com/news/articles/2017-09-22/imagination-technologies-agrees-to-takeover-by-canyon-bridge
  • Valentin,
    Welcome!
    Peter (Tachyon fame, and in Brisbane) and I have iCE40UP5K QFN48 boards. I have Lattices iCExxx2 sw compiling some simple demo code. Haven't tried downloading yet, or getting P1V compiling either.
    I love building hw too.

    Liz had her knees done just over 2 weeks ago. She's progressing extremely fast. Running after is still taking most of my time ;)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • PM sent to Valentin.
  • KeithE,

    Where are you reading news of project IceStorm having stalled?

    Admittedly the projects web page has not been updated since March but commits are still happening on github.
    I'm not sure what Adafruit has got to do with IceStorm.

    For once I'm happy with a Trump move, blocking the sale of Lattice to China.
  • KeithEKeithE Posts: 883
    edited October 4 Vote Up0Vote Down
    Heater. wrote: »
    KeithE,
    Where are you reading news of project IceStorm having stalled?

    I was only referring to "Icestorm support of the iCE40 Ultra parts (by Adafruit employee)" which was being worked on by tannewt from Adafruit. You made me search, and I couldn't find the reference where I saw this being referred to as stalled, but this is in the main ultra thread:

    https://github.com/cliffordwolf/icestorm/issues/68

    "tannewt commented on Aug 1
    Thanks for the heads up @cliffordwolf. I'm not exactly sure when I'll pick it up again. I'll be a lot more interested when chips are more readily available. Thanks!"

    Then people point out that the parts are available, but no response.
  • Basman74Basman74 Posts: 7
    edited October 4 Vote Up0Vote Down
    Cluso99 wrote: »
    Valentin,
    Welcome!
    Peter (Tachyon fame, and in Brisbane)
    Ah right. Sorry Peter (Really like your work! :-)

    Cluso99 wrote: »
    I have iCE40UP5K QFN48 boards. I have Lattices iCExxx2 sw compiling some simple demo code.
    Nice. I initially dived into Lattice's MachXO2 (4k and 7k variants) a few years ago when I really wanted to get into FPGAs more..

    Cluso99 wrote: »
    Liz had her knees done just over 2 weeks ago. She's progressing extremely fast. Running after is still taking most of my time ;)
    Glad to hear! I find it amazing how routine those procedures have become..


    @ ozpropdev / Tubular: Thanks for the welcome messages lads. Nice to feel included :-)
    @ rogloh: Will reply to your PM in detail tomorrow.

    Cheers,
    Valentin

  • Hello Valentin

    Welcome to this forum. We already chatted per Email when I bought one of your FleaUno boards. Still one of my preferred FPGA boards.

    I really hope your Indiegogo campaign will be successfull, and for sure I will buy one because I know that your USB Interface and driver to program the Lattice FPGAs works well and is easy to use.
    Your board seems to be the only available cheap Evaluation board for ECP5 so far.

    cheers
    Andy (from Insonix)
  • Nice to see you overe here, Valentin.
    I have two of your boards - I don't remember if I got both or just one of them sent to Japan.
    You'll fit right in with the Propeller gang. I admit I still find FPGA programming a bit heavy-duty -- it's just so much easier to program the Propeller to play various hw roles.
    -Tor
  • cgraceycgracey Posts: 8,297
    edited October 4 Vote Up0Vote Down
    Welcome, Valentin!
  • Basman74Basman74 Posts: 7
    edited October 5 Vote Up0Vote Down
    @ Ariba / Tor
    Thanks guys. I see you are both fans of the propeller too (no pun intended).

    @ cgracey
    Thanks Chip! I've been a long-standing admirer (from afar) of your highly inspirational work. From what I've seen of the latest specs on your upcoming Prop-2, it's going to be an absolute screamer! :)

    Cheers,
    Valentin
  • Hello Valentin!

    I recently backed your FleaFPGA Ohm project on Indiegogo, telling you that I intend to use one out of two boards to run Minimig and Music-X sequencer... well, now you discovered my dirty secret, the second board is for P1V! :D

    Welcome!
    Alessandro
  • yetiyeti Posts: 339
    edited October 5 Vote Up0Vote Down
    KeithE wrote: »
    https://github.com/cliffordwolf/icestorm/issues/68

    "tannewt commented on Aug 1
    Thanks for the heads up @cliffordwolf. I'm not exactly sure when I'll pick it up again. I'll be a lot more interested when chips are more readily available. Thanks!"

    Then people point out that the parts are available, but no response.
    I have such a US$8-board (soon 2), so their availability definitely is proven... ;-)

    Now hoping for Icestorm supporting them someday.

    For me it's not urgent because I'm just starting to look at FPGAs with Lattices's HX8K boards. I still have long way to go from zero to interesting cores in FPGAs.
    Windows.
    No Source – No Go!
    Please help: http://rosettacode.org/wiki/Category:Spin
    Why Asimov's Laws of Robotics Don't Work - Computerphile
    DNA is a four letter word.
  • Basman74Basman74 Posts: 7
    edited October 7 Vote Up0Vote Down
    I recently backed your FleaFPGA Ohm project on Indiegogo, telling you that I intend to use one out of two boards to run Minimig and Music-X sequencer... well, now you discovered my dirty secret, the second board is for P1V! :D

    Aha! :D

    It's ok Alessandro, I won't tell anyone else.. I promise. ;)

    Cheers,
    Valentin
  • So today I got interested in trying out the Lattice FPGA tools with P1V and downloaded the latest 3.10 Lattice Diamond software for my Ubuntu machine with the free license. This OS not officially supported and I should be using RHEL but I was able to follow a couple of things I found online to get it to install/run on my system. Never used Lattice stuff before this, only Quartus.

    I grabbed Jac Goudsmit's P1V codebase which is somewhat more portable now than the original code and proceeded to import it into a Lattice Project targeting an ECP5 LFE5U25 part (containing ~24k LUTs).

    Even though the P1V is not yet fully integrated with the Lattice part (eg. I don't have a PLL setup yet, IO pin assignments are not setup, nor any proper timing constraints etc), I was at least able to get the Verilog code synthesized, mapped and placed (with plenty of warnings, but no errors) to get some basic idea of the resource usage of a P1V on this FPGA. How accurate this really is without the final project fully setup correctly, I don't know but here is some information that could be useful for ballpark usage figures...take it with a grain of salt for now.

    On my >10 year old dual core PC it took about 5mins for synthesis, 45s to map it, and place and route took about 5min40s. This is probably somewhat faster than what the DE0-nano build takes for my system with Quartus.

    Here's some of the report output it generated related to resources...and it seems like it only uses about 75% of the device for 8 COGs which is nice. At this point I have no idea about the timing performance of these parts, hopefully they can reach a minimum of 80MHz core speed for P1V or higher. I will need to learn more about the tools to understand how to set it up more and also follow the report information. I do know the ROM initialization bit didn't work as it couldn't find the hex file in the $readmemh instructions - hopefully just a bad file path setup as I wasn't sure where to locate these hex files yet.
    Design Summary
       Number of registers:   5431 out of 24642 (22%)
          PFU registers:         5431 out of 24288 (22%)
          PIO registers:            0 out of   354 (0%)
       Number of SLICEs:      9167 out of 12144 (75%)
          SLICEs as Logic/ROM:   9167 out of 12144 (75%)
          SLICEs as RAM:            0 out of  9108 (0%)
          SLICEs as Carry:       1007 out of 12144 (8%)
       Number of LUT4s:        15366 out of 24288 (63%)
          Number used as logic LUTs:        13352
          Number used as distributed RAM:     0
          Number used as ripple logic:      2014
          Number used as shift registers:     0
       Number of PIO sites used: 42 out of 118 (36%)
       Number of block RAMs:  24 out of 56 (43%)
       Number of GSRs:  0 out of 1 (0%)
       JTAG used :      No
       Readback used :  No
       Oscillator used :  No
       Startup used :   No
       DTR used :   No
       Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
       Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
       Number of DCC:  0 out of 60 (0%)
       Number of DCS:  0 out of 2 (0%)
       Number of PLLs:  0 out of 2 (0%)
       Number of DDRDLLs:  0 out of 4 (0%)
       Number of CLKDIV:  0 out of 4 (0%)
       Number of ECLKSYNC:  0 out of 10 (0%)
       Number of ECLKBRIDGECS:  0 out of 2 (0%)
       Notes:-
          1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
         distributed RAMs) + 2*(Number of ripple logic)
          2. Number of logic LUT4s does not include count of distributed RAM and
         ripple logic.
    
            Number Of Mapped DSP Components:
       --------------------------------
       MULT18X18D          0
       MULT9X9D            0
       ALU54B              0
       ALU24B              0
    
       PRADD18A            0
       PRADD9A             0
       --------------------------------
       Number of Used DSP MULT Sites:  0 out of 56 (0 %)
       Number of Used DSP ALU Sites:  0 out of 28 (0 %)
       Number of Used DSP PRADD Sites:  0 out of 56 (0 %)
       Number of clocks:  3
         Net clock_50_c: 2265 loads, 2265 rising, 0 falling (Driver: PIO clock_50 )
         Net clk_cog: 32 loads, 32 rising, 0 falling (Driver: clkgen/divide[12] )
         Net clk_pll_0: 832 loads, 832 rising, 0 falling (Driver: clkgen/clk_pll_0 )
    
    <..snip..>
    
    Device utilization summary:
    
       PIO (prelim)      42/197          21% used
                         42/118          35% bonded
    
       SLICE           9167/12144        75% used
    
       EBR               24/56           42% used
    
    
    Number of Signals: 19922
    Number of Connections: 66677
    
    Pin Constraint Summary:
       0 out of 42 pins locked (0% locked).
    
    The following 3 signals are selected to use the primary clock routing resources:
        clock_50_c (driver: clock_50, clk/ce/sr load #: 2265/0/0)
        clk_pll_0 (driver: clkgen/SLICE_9269, clk/ce/sr load #: 832/0/0)
        clk_cog (driver: SLICE_5579, clk/ce/sr load #: 32/0/0)
    
    

    Roger.


  • rogloh wrote: »
    ....
    Even though the P1V is not yet fully integrated with the Lattice part (eg. I don't have a PLL setup yet, IO pin assignments are not setup, nor any proper timing constraints etc), I was at least able to get the Verilog code synthesized, mapped and placed (with plenty of warnings, but no errors) to get some basic idea of the resource usage of a P1V on this FPGA. How accurate this really is without the final project fully setup correctly, I don't know but here is some information that could be useful for ballpark usage figures...take it with a grain of salt for now.
    Very useful numbers, shows an easy fit into LFE5U-25, but probably too large for LFE5U-12, until some serious optimize work is done..
    The LFE5U-25 is still sub $10 and showing the 10mm 285BGA parts due in December...


    What were the option settings for the source ? - IIRC some video blocks could be disabled to shrink size somewhat.

    Interesting the LUT4 is 63%, but SLICE is 75%, even with 8% used for Carry, that's still 4% more - maybe its a routing thing ?

  • Nice going Roger

    Coincidentally Mouser now have the 10x10mm variant of the LFE5U-25 in stock, found this out because they shipped my backorder to me yesterday.

    Having a decent LE size (25, 45, 85k) in a 10x10mm is just great. That was the problem with the 10M08SAU169's being only available in 8k and 16k LE and nothing beyond that.

    Really excited to see what MHz they will do.

    I started playing with layouts as you can see from pic below. 10x10mm is just that little bit nicer than 11x11.
    1063 x 331 - 12K
  • Tubular wrote: »
    I started playing with layouts as you can see from pic below. 10x10mm is just that little bit nicer than 11x11.

    Interesting, if you use enough layers, maybe the skipped pins can be 'smd' soldered.
    We used to do that with programming adapters, most pins were thru-hole, but some that conflicted near the central socket either bent, or SMD mounted.
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