Streamer "gotcha" and INB issue

Hi Chip
I've encountered a couple of issues while using the streamer.
The "gotcha" was an example of incorrect use by me of the hub FIFO.
In the P2 documentation the following statement is made.
There are three ways the hub FIFO interface can be used, and it can only be used for one of these, at a time:

Maybe an additional warning needs to be added to the docs along the lines of:
You CANNOT issue a WRFAST instruction while in hubexec mode.
This will cause code execution to cease.

This had me wheel spinning (or should that be cog spinning) for a while :)

The second issue I found was when trying to capture the top 8 bits of INB, the
lower nibble is incorrect. Diving into it deeper I discovered that the same issue occurs
when reading INB. Pins 59..56 outputs work OK but can't be read.
The code below was used to test all pins.
'toggle a pin an read its state back

	sys_clk = 80_000_000

	led = 32
	pin = 56			'pin to test

dat		org

		setb	dirb,#led	'enable status led
		mov	adra,#pin
		testb	adra,#5 wc
	if_nc	setb	dira,#pin	'set pin as output
	if_c	setb	dirb,#pin
.loop	if_nc	notb	outa,#pin	'toggle pin
	if_c	notb	outb,#pin
		waitx	##sys_clk / 4
	if_nc	testb	ina,#pin wz	'read pin
	if_c	testb	inb,#pin wz
		setbz	outb,#led	'update status
		jmp	#.loop

Cheers
Brian

Comments

  • I assume you have a Prop123-A9 board.

    In order to hook up more hardware to P0..P63, some pins' outputs and inputs go different places. In your case, P63 is reading the RX signal from the USB chip and P59..P56 are reading the three pushbuttons PB3..PB0.

    I'm sorry this wasn't documented.

    About the WRFAST during hub execution: That will blow things up, for sure. So should any of those related instructions. I'm adding a bit to the documentation now to cover this.
  • Thanks Chip!
    A quick look at the schematic shows a 10K pullup on the push buttons.
    I assumed outputting to those pins would be OK.
    What tricked me was the fact that P59..P56 on the header show the expected waveforms on the scope.
    Looking at the schematic again I now see that P59.P56 have dual assignments on the FPGA.
    It appears that outputs for these pins is on the header and the inputs are mapped to the push buttons.
    It all makes sense now...:)
    Cheers
    brian

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