release date
HYDRAGON
Posts: 1
in Propeller 2
When will the propellor 2 be released?.
Comments
We've all been through this a couple of times ... design ... testing ... chip test runs ... failure. The chip has been redesigned several times and benefitted from the process each time. Currently you can download (from this forum) an FPGA-based version of the core (cogs, hub, memories, etc.) and experiment with it. There'll be some small changes / corrections yet to be made, but it's essentially done. The "smart I/O pins" are still to be implemented for the FPGA version, but these have been designed before and won't take long (probably weeks). This'll all have to be tested in the FPGA version. Then the process of coming up with the actual chip design and tuning it for efficiency and reliability will take a while ... a test run or two of actual chips, maybe some tweeking. Probably some time in 2016 ... not early ... and this is just my relatively uninformed opinion. Your mileage may vary.
Or much better suggestion !! : Can the P2 forum be read-only, and read-write just to the 6 or 7 guys that have the P1-2-3 board?
Chip, had a lot of feedback and good ideas from a lot of smart and experienced programmers, and the result was great.
However I think than once the fpga release is done, the work must be just testing.
So that is why I think a small period of testing without suggesting new ideas will help.
After that, smartpins, right?
Hello Ramon,
This isn't something I'd want to do. It effectively closes off our work from the rest of the world, which is opposite of the open design effort we need to establish some core users before the P2 is fabricated.
But I understand why you'd suggest this - it should take a load off of Chip in his communication demands.
Ken Gracey
Ramon, do you have an FPGA board of any type, already? I think the next board to support would be the DE0-Nano. It could do two cogs without the CORDIC solver.
What is all this about closing the the thread to the elite only?
Imho, it is better to address it and continue on. There have been some good ideas.
I could do testing on a Nano or two (much more portable that 123 or DE2). I'm not smart enough to use that CORDIC kerfluffle machine anyway!
Whatever restrictions that fit is fine by me.
Who is in charge of the test plan?
-Tor
At some point I'd like to see an image for the smaller boards as these are ones that I can afford to throw to the wolves when it comes to testing hardware configurations. Obviously of course, when an image proves stable enough it would be a good time to port to the DE0 to open up testing to more participants anyway.
At this point can I make a request/plea that these threads that are being "spammed" to put it politely be moderated or closed off only for releases if it's about releases, only for bugs, if it's about bugs etc so we don't have to sift through the last 100 messages since yesterday to find what is actually relevant, hence my use of the word "spam" since the posters are not respecting the thread titles by moving elsewhere.
Closing it down will slow the progress.
Splitting threads is a feature available to moderators. If you ever find a thread worthy of splitting, just flag the thread for moderator review* and make a note where you'd like the split to occur (and perhaps a new title too!). We have limited time resources and can't promise to always agree with the requests either
(* Use the Report Forum Spam feature) - or send me a PM, or whilst it remains in service, post to the Activity wall !
That would be Heater. I have already tested the P2 and found it to be perfect. Heater is the only one on the fence right now:)
Rich
Test plan? Who and What? ...good question.
I am not a P1 wizard. Will need guidance.
Closing the P2 forum only to board testers is not a good suggestion. True, but I think there are some periods in which some limit is needed. It doesn't need to be permanent. Can be enabled for one or two weeks, and later disabled.
Look what is happening right now. Chip is trying find TIME to document the new design, change the spin/asm tools, and release fpga images for other boards. How can he do all of that while he read 80 messages a day?
Maybe some temporary policy can be implemented, like assigning a quota? (allow no more than x messages per day, or no more than x characters per day). Will this system teach us self-moderation? This system looks completely automatic and fair.
He was 42.
But we can't do that without resolving a few very basic things. If we don't do that, and we rush forward, the multiplier of having to go back and recode / redo becomes a real burden very quickly. This is also why Chip has limited the features being documented for discussion. It's too early, and there are too many dependencies on those.
Looks like addressing is resolved now, so now we go forward. People will write some code, and they will be happy, can live with it, or not...
That process isn't pretty. But it is necessary.
Chip isn't doing long hours on messages. Those don't take long. He's doing long hours implementing the things that make sense given the discussion here.
Without that discussion, there really isn't the same level of implementation and he's made it clear that level is the target of the project.
Remember, novel things are novel. This kind of thing happens. We are almost past low level discussions. Once we have that foundation, things will advance much more quickly with larger chunks of code, etc... being done. But that foundation has to be solid, or we all lose out.
Some examples of what needs to come, but can't yet due to the very core things being unresolved: ROM code, booter, monitor, crypt, etc... some test / debug template type code, etc... serial, video, and other core bits.
We've got little chunks of that, and those have been rewritten a time or two. Addressing was hard! (and it may still be, but it's looking favorable now)
Lots to think about. And some of that thinking required we actually write some code, bonk our heads on it, and then bring those experiences back for resolution too.
When we did "hot", Chip moved past this stage and we jumped in at that point. It moved more quickly, but then we stalled hard on some basics that really could have been done earlier. Factor out that it was actually "hot" and just look at the design process at that time. We took a big step forward, then struggled with some basics.
So this time, the basics are taking a bit longer, but the net should be a better design without the refactors that were going on before.
Relax. It's about to kick up a notch.
Threads are Threads....
If you want to track what's new, that's usually updated in the top release post, and if you want to not lose bugs, why not start a separate bug thread, as others do already ?
Possibly bug threads could sink as they are resolved ? (or be tagged solved by the author?)
DE0 nano waiting here. All fired up, no place to go !
Still impatiently waiting for Chipmas....
@jmg,
Threads is threads. My name was mentioned so here I am.
If there are FPGA releases coming out there really needs to be an issue reporting/tracking system where issues can be kept orderly. Perhaps Chip could spend 10 minutes putting up a PII repo on github. Even if it has nothing in it but the FPGA images it would provide an issue tracker for feed back and discussion of any bugs. Also a good place to keep documentation.
Where can I get any information to get a running start for when it become available?
I use both SPIN and PASM.
http://forums.parallax.com/categories/propeller-2-multicore-microcontroller
It's hard to summarize in a few sentences.