Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

15152545657160

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  • WOOOHOOO!!!

    Possible Chipmass in July :) :) :)
    cgracey wrote: »
    David Betz wrote: »
    cgracey wrote: »
    David Betz wrote: »
    What ever happened to the May shuttle? Did the P2 test make it?

    It's being fabricated now. It's all the analog stuff involving the pad frame. There is no synthesized core logic. We're just interested in proving the pins, at this point.
    Sounds like an important step forward though. When do you expect to get chips?

    Probably end of July.

  • Cluso99Cluso99 Posts: 16,185
    edited 2016-06-16 - 05:17:16
    cgracey wrote: »
    Cluso99 wrote: »
    Cannot wait to see real silicon :)

    Did you manage to get anywhere with the BeMicroCV-A9? I've had a few too many things on my plate to sort out any details but I think Chip said he would do an image for it, he just needs a pinout.

    I just need a pin out for it.
    Please see second post below for further discussion!!!
    Chip,
    Is this what you need?
    "BeMicro CV-A9 Board"
                                
    set_global_assignment -name DEVICE 5CEFA9F23C8N
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name TOP_LEVEL_ENTITY top
    set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2"
    set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:54  OCTOBER 05, 2012"
    set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
    set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
    
    set_location_assignment PIN_H13 -to clock_50
    set_location_assignment PIN_M9  -to clock_24
    set_location_assignment PIN_    -to clock_in_out
    set_location_assignment PIN_    -to clock1_in
    set_location_assignment PIN_    -to clock1_out
    set_location_assignment PIN_    -to clock2_in
    set_location_assignment PIN_    -to clock2_out
    
    set_location_assignment PIN_V10 -to p[0]
    set_location_assignment PIN_P8  -to p[1]
    set_location_assignment PIN_Y10 -to p[2]
    set_location_assignment PIN_Y9  -to p[3]
    set_location_assignment PIN_R12 -to p[4]
    set_location_assignment PIN_P12 -to p[5]
    set_location_assignment PIN_AB10 -to p[6]
    set_location_assignment PIN_AB11 -to p[7]
    set_location_assignment PIN_B17 -to p[8]   
    set_location_assignment PIN_E19 -to p[9]   
    set_location_assignment PIN_E21 -to p[10]  
    set_location_assignment PIN_B21 -to p[11]  
    set_location_assignment PIN_C20 -to p[12]  
    set_location_assignment PIN_C21 -to p[13]  
    set_location_assignment PIN_D19 -to p[14]  
    set_location_assignment PIN_D21 -to p[15]  
    set_location_assignment PIN_H18 -to p[16]
    set_location_assignment PIN_J18 -to p[17]
    set_location_assignment PIN_C16 -to p[18]
    set_location_assignment PIN_D17 -to p[19]
    set_location_assignment PIN_G17 -to p[20]
    set_location_assignment PIN_E16 -to p[21]  
    set_location_assignment PIN_P16 -to p[22]
    set_location_assignment PIN_P17 -to p[23]
    set_location_assignment PIN_M22 -to p[24]  
    set_location_assignment PIN_W9  -to p[25]  
    set_location_assignment PIN_U6  -to p[26]  
    set_location_assignment PIN_V6  -to p[27]  
    set_location_assignment PIN_U7  -to p[28]  
    set_location_assignment PIN_U8  -to p[29]  
    set_location_assignment PIN_    -to p[30]
    set_location_assignment PIN_    -to p[31]
    set_location_assignment PIN_R11 -to p[32]
    set_location_assignment PIN_R10 -to p[33]
    set_location_assignment PIN_U12 -to p[34]
    set_location_assignment PIN_U11 -to p[35]
    set_location_assignment PIN_R9  -to p[36]
    set_location_assignment PIN_T10 -to p[37]
    set_location_assignment PIN_U10 -to p[38]
    set_location_assignment PIN_T9  -to p[39]
    set_location_assignment PIN_N16 -to p[40]
    set_location_assignment PIN_M16 -to p[41]
    set_location_assignment PIN_N19 -to p[42]
    set_location_assignment PIN_M18 -to p[43]
    set_location_assignment PIN_K17 -to p[44]
    set_location_assignment PIN_L17 -to p[45]
    set_location_assignment PIN_L19 -to p[46]
    set_location_assignment PIN_L18 -to p[47]
    set_location_assignment PIN_T18 -to p[48]
    set_location_assignment PIN_T17 -to p[49]      
    set_location_assignment PIN_Y11 -to p[50]  
    set_location_assignment PIN_AA12 -to p[51] 
    set_location_assignment PIN_AA8 -to p[52]  
    set_location_assignment PIN_AB8 -to p[53]  
    set_location_assignment PIN_T19 -to p[54]  
    set_location_assignment PIN_T20 -to p[55]  
    set_location_assignment PIN_T22 -to p[56]  
    set_location_assignment PIN_P21 -to p[57]  
    set_location_assignment PIN_R22 -to p[58]  
    set_location_assignment PIN_P22 -to p[59]  
    set_location_assignment PIN_T15 -to p[60]     
    set_location_assignment PIN_R15 -to p[61]     
    set_location_assignment PIN_R16 -to p[62]     
    set_location_assignment PIN_R17 -to p[63]
    
    set_location_assignment PIN_AA9 -to fpga_resn  
    set_location_assignment PIN_    -to fpga_rx
    set_location_assignment PIN_    -to fpga_tx
    

  • Cluso99Cluso99 Posts: 16,185
    edited 2016-06-16 - 05:17:32
    Please see second post below for further discussion!!!
    This is what I had worked out for the pinout before. Cannot recall if the other boards are correct, but it is what I was proposing for the BeMicro CV-A9.

    fpga_pinouts4.jpg
    1154 x 428 - 239K
  • I have just been rechecking what Chip did for the BeMicroCV-A2.
    Here is the pinout, and a discussion for the BeMicroCV-A9.
    Note it is different to the above 2 posts!!!

    On the A9 some pins are not available as I/O. These are in yellow.
    Should we try and keep the connections the same where possible???

    This means that for P0..P35, both P18 & P19 are not available in A9. Does it matter?

    Also, the PropPlug does not fit in the same location as P62 is missing.
    Where should we put it? Does it need to plug straight in? If so, perhaps replacing P27/P29/P31 with RESn/P63/P62?
  • Forgot the attachment :(BeMicroCV-A2-A9%20pinout%20discussion.jpg

    LED and SD connections need rechecking.
  • TubularTubular Posts: 3,955
    edited 2016-06-16 - 05:46:13
    I looked at this earlier and concluded that because the prop plug had to move anyway, its not worth thinking too hard about. I was looking at whether having the same Pin numbers as the DE0-Nano at least on J1

    It probably makes sense to take internal DAC signals out via the 80 pin connector. It may make sense to also bring out the other pins that the CV A9 cannot breakout
  • I just posted a new v10 at the top of this thread. This version is like the prior, but contains the new global asynchronous reset on all flops, to facilitate scan insertion when we synthesize the final ASICs. Please try it out, just to make sure nothing has changed. Thanks!
  • Cluso99Cluso99 Posts: 16,185
    edited 2016-06-16 - 06:44:15
    Chip,
    Could you post the BeMico CV A2 config file and I will modify it for the A9 version please.

    BTW Did you ask OnSemi about Flash/OTP/EEPROM ?
  • BeMicro CV-A9 users...
    What do you think about adding a wire to the A9 board connector J4 Pins 38 to 39 ?
    I can make 38 = P62 and then the PropPlug would fit in the same position as the A2 version.
    Does anyone require P58..P61 for trying SPI Flash?

  • Peter JakackiPeter Jakacki Posts: 9,096
    edited 2016-06-16 - 06:55:29
    Cluso99 wrote: »
    BeMicro CV-A9 users...
    What do you think about adding a wire to the A9 board connector J4 Pins 38 to 39 ?
    I can make 38 = P62 and then the PropPlug would fit in the same position as the A2 version.
    Does anyone require P58..P61 for trying SPI Flash?

    I'm just about to get back into looking at the pinouts and I am definitely wanting to use SPI boot Flash but also I want to use the 80-pin edge connector mainly alhtough I am flexible in this regard. The exact position of the PropPlug doesn't really matter as it is also easy enough to run individual jumper wires to the correct pins.

    The reason for the edge connector and Flash is that I will be upgrading Tachyon for this board and using it in a current project. However I will also implement VGA along with the SD FAT32 I already have and the WIZnet servers so that I can have a full stand-alone development system. I have an inline assembler that I will upgrade as well so by just adding a keyboard and a text editor I'm ready.

    BTW, you can use this standalone system simply as a platform to further develop your own compilers etc.

  • Cluso99 wrote: »
    Chip,
    Could you post the BeMico CV A2 config file and I will modify it for the A9 version please.

    BTW Did you ask OnSemi about Flash/OTP/EEPROM ?

    Sorry. I still haven't asked. All my focus has been on the Verilog and scan insertion. I will, soon, though.

    Meanwhile, here's that BeMicro A2 .qsf file:
    set_global_assignment -name DEVICE 5CEFA2F23C8
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name TOP_LEVEL_ENTITY top
    set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2"
    set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:54  OCTOBER 05, 2012"
    set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
    set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
    
    set_location_assignment PIN_H13 -to clock_50
    
    set_location_assignment PIN_N1 -to led[7]
    set_location_assignment PIN_N2 -to led[6]
    set_location_assignment PIN_U1 -to led[5]
    set_location_assignment PIN_U2 -to led[4]
    set_location_assignment PIN_W2 -to led[3]
    set_location_assignment PIN_AA1 -to led[2]
    set_location_assignment PIN_AA2 -to led[1]
    set_location_assignment PIN_Y3 -to led[0]
    
    set_location_assignment PIN_C16 -to dip_sw[1]
    set_location_assignment PIN_D17 -to dip_sw[2]
    set_location_assignment PIN_G17 -to dip_sw[3]
    
    set_location_assignment PIN_H18 -to s[1]
    set_location_assignment PIN_J18 -to s[2]
    
    # j4 pins
    set_location_assignment PIN_G1 -to p[36]
    set_location_assignment PIN_G2 -to p[37]
    set_location_assignment PIN_V10 -to p[38]
    set_location_assignment PIN_P8 -to p[39]
    set_location_assignment PIN_R7 -to p[40]
    set_location_assignment PIN_P7 -to p[41]
    set_location_assignment PIN_W8 -to p[42]
    set_location_assignment PIN_W9 -to p[43]
    set_location_assignment PIN_U6 -to p[44]
    set_location_assignment PIN_V6 -to p[45]
    set_location_assignment PIN_U7 -to p[46]
    set_location_assignment PIN_U8 -to p[47]
    set_location_assignment PIN_AA7 -to p[48]
    set_location_assignment PIN_AB7 -to p[49]
    set_location_assignment PIN_AB6 -to p[50]
    set_location_assignment PIN_AB5 -to p[51]
    set_location_assignment PIN_AA8 -to p[52]
    set_location_assignment PIN_AB8 -to p[53]
    set_location_assignment PIN_AA10 -to p[54]
    set_location_assignment PIN_AA9 -to p[55]
    set_location_assignment PIN_Y10 -to p[56]
    set_location_assignment PIN_Y9 -to p[58]
    
    set_location_assignment PIN_R12 -to resn_pin
    set_location_assignment PIN_P12 -to p[59]
    set_location_assignment PIN_AB10 -to p[63]
    set_location_assignment PIN_AB11 -to p[60]
    set_location_assignment PIN_Y11 -to p[62]
    set_location_assignment PIN_AA12 -to p[61]
    
    # j1 pins
    set_location_assignment PIN_R11 -to p[0]
    set_location_assignment PIN_R10 -to p[1]
    set_location_assignment PIN_U12 -to p[2]
    set_location_assignment PIN_U11 -to p[3]
    set_location_assignment PIN_R9 -to p[4]
    set_location_assignment PIN_T10 -to p[5]
    set_location_assignment PIN_U10 -to p[6]
    set_location_assignment PIN_T9 -to p[7]
    set_location_assignment PIN_N16 -to p[8]
    set_location_assignment PIN_M16 -to p[9]
    set_location_assignment PIN_N19 -to p[10]
    set_location_assignment PIN_M18 -to p[11]
    set_location_assignment PIN_K17 -to p[12]
    set_location_assignment PIN_L17 -to p[13]
    set_location_assignment PIN_L19 -to p[14]
    set_location_assignment PIN_L18 -to p[15]
    set_location_assignment PIN_T18 -to p[16]
    set_location_assignment PIN_T17 -to p[17]
    set_location_assignment PIN_T19 -to p[18]
    set_location_assignment PIN_T20 -to p[19]
    set_location_assignment PIN_K21 -to p[20]
    set_location_assignment PIN_K22 -to p[21]
    set_location_assignment PIN_M20 -to p[22]
    set_location_assignment PIN_M21 -to p[23]
    set_location_assignment PIN_M22 -to p[24]
    set_location_assignment PIN_L22 -to p[25]
    set_location_assignment PIN_N20 -to p[26]
    set_location_assignment PIN_N21 -to p[27]
    set_location_assignment PIN_P22 -to p[28]
    set_location_assignment PIN_R17 -to p[29]
    set_location_assignment PIN_R21 -to p[30]
    set_location_assignment PIN_R16 -to p[31]
    set_location_assignment PIN_R22 -to p[32]
    set_location_assignment PIN_R15 -to p[33]
    set_location_assignment PIN_T22 -to p[34]
    set_location_assignment PIN_T15 -to p[35]
    
    # missing pin
    set_location_assignment PIN_L7 -to p[57]
    
    
    set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
    set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
    set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
    set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
    
    set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
    set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
    set_global_assignment -name SEED 1
    
    set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
    set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
    set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
    set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
    set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
    set_global_assignment -name FITTER_EFFORT "AUTO FIT"
    set_global_assignment -name SAVE_DISK_SPACE OFF
    set_global_assignment -name SMART_RECOMPILE ON
    set_global_assignment -name QII_AUTO_PACKED_REGISTERS AUTO
    set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
    set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
    set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ON
    set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE PARALLEL X8"
    set_global_assignment -name GENERATE_RBF_FILE ON
    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
    set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
    set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
    set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
    set_global_assignment -name ALLOW_REGISTER_MERGING ON
    set_global_assignment -name ENABLE_OCT_DONE OFF
    set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
    set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
    set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
    set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
    set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    set_global_assignment -name SYSTEMVERILOG_FILE pin_pgm_original.sv
    set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to resn_pin
    
    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
    
  • Thanks Chip,
    I will get onto it now. I will place the PropPlug in the same location as the A2 version, with a jumper on the A9 required or else use separate wires to the PropPlug which is easy as.
    I will do a pic of the board with pinouts too (as you did for the other boards).
  • In regards to the CV-A9, if we can boot off the microSD then we needn't worry about SPI Flash if that makes it easier. What was decided about booting off SD? Something simple I hope, like just booting from sector 0 etc.
  • Cluso99 wrote: »
    Thanks Chip,
    I will get onto it now. I will place the PropPlug in the same location as the A2 version, with a jumper on the A9 required or else use separate wires to the PropPlug which is easy as.
    I will do a pic of the board with pinouts too (as you did for the other boards).

    Super!
  • Chip,
    Here is the BeMicroCV-A9.qsf file.
    set_global_assignment -name DEVICE 5CEFA9F23C8N
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name TOP_LEVEL_ENTITY top
    set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2"
    set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:54  OCTOBER 05, 2012"
    set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
    set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
    
    set_location_assignment PIN_H13 -to clock_50
    
    set_location_assignment PIN_D21 -to led[7]
    set_location_assignment PIN_D19 -to led[6]
    set_location_assignment PIN_C21 -to led[5]
    set_location_assignment PIN_C20 -to led[4]
    set_location_assignment PIN_B21 -to led[3]
    set_location_assignment PIN_E21 -to led[2]
    set_location_assignment PIN_E19 -to led[1]
    set_location_assignment PIN_B17 -to led[0]
    
    set_location_assignment PIN_C16 -to dip_sw[1]
    set_location_assignment PIN_D17 -to dip_sw[2]
    set_location_assignment PIN_G17 -to dip_sw[3]
    
    set_location_assignment PIN_H18 -to s[1]
    set_location_assignment PIN_J18 -to s[2]
    
    # j4 pins
    //set_location_assignment PIN_G1 -to p[36]
    //set_location_assignment PIN_G2 -to p[37]
    set_location_assignment PIN_V10 -to p[38]
    set_location_assignment PIN_P8 -to p[39]
    set_location_assignment PIN_R7 -to p[40]
    set_location_assignment PIN_P7 -to p[41]
    set_location_assignment PIN_W8 -to p[42]
    //set_location_assignment PIN_W9 -to p[43]
    //set_location_assignment PIN_U6 -to p[44]
    //set_location_assignment PIN_V6 -to p[45]
    //set_location_assignment PIN_U7 -to p[46]
    //set_location_assignment PIN_U8 -to p[47]
    //set_location_assignment PIN_AA7 -to p[48]
    //set_location_assignment PIN_AB7 -to p[49]
    //set_location_assignment PIN_AB6 -to p[50]
    //set_location_assignment PIN_AB5 -to p[51]
    //set_location_assignment PIN_AA8 -to p[52]
    //set_location_assignment PIN_AB8 -to p[53]
    set_location_assignment PIN_AA10 -to p[58]
    //set_location_assignment PIN_AA9 -to p[54]
    set_location_assignment PIN_Y10 -to p[59]
    set_location_assignment PIN_Y9 -to p[60]
    
    set_location_assignment PIN_R12 -to resn_pin
    set_location_assignment PIN_P12 -to p[61]
    set_location_assignment PIN_AB10 -to p[63]
    set_location_assignment PIN_AB11 -to p[62]
    //set_location_assignment PIN_Y11 -to p[55]
    //set_location_assignment PIN_AA12 -to p[56]
    
    # j1 pins
    set_location_assignment PIN_R11 -to p[0]
    set_location_assignment PIN_R10 -to p[1]
    set_location_assignment PIN_U12 -to p[2]
    set_location_assignment PIN_U11 -to p[3]
    set_location_assignment PIN_R9 -to p[4]
    set_location_assignment PIN_T10 -to p[5]
    set_location_assignment PIN_U10 -to p[6]
    set_location_assignment PIN_T9 -to p[7]
    set_location_assignment PIN_N16 -to p[8]
    set_location_assignment PIN_M16 -to p[9]
    set_location_assignment PIN_N19 -to p[10]
    set_location_assignment PIN_M18 -to p[11]
    set_location_assignment PIN_K17 -to p[12]
    set_location_assignment PIN_L17 -to p[13]
    set_location_assignment PIN_L19 -to p[14]
    set_location_assignment PIN_L18 -to p[15]
    set_location_assignment PIN_T18 -to p[16]
    set_location_assignment PIN_T17 -to p[17]
    //set_location_assignment PIN_T19 -to p[33]
    //set_location_assignment PIN_T20 -to p[35]
    set_location_assignment PIN_Y11 -to p[18]
    set_location_assignment PIN_AA12 -to p[19]
    set_location_assignment PIN_AA8 -to p[20]
    set_location_assignment PIN_AB8 -to p[21]
    set_location_assignment PIN_T19 -to p[22]
    set_location_assignment PIN_T20 -to p[23]
    set_location_assignment PIN_T22 -to p[24]
    set_location_assignment PIN_AA9 -to p[25]
    set_location_assignment PIN_P21 -to p[26]
    set_location_assignment PIN_R17 -to p[27]
    set_location_assignment PIN_R22 -to p[28]
    set_location_assignment PIN_R16 -to p[29]
    set_location_assignment PIN_P22 -to p[30]
    set_location_assignment PIN_R15 -to p[31]
    //set_location_assignment PIN_T22 -to p[34]
    set_location_assignment PIN_T15 -to p[32]
    
    # missing pin
    set_location_assignment PIN_L7 -to p[57]
    
    
    set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
    set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
    set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
    set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
    
    set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
    set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
    set_global_assignment -name SEED 1
    
    set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
    set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
    set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
    set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
    set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
    set_global_assignment -name FITTER_EFFORT "AUTO FIT"
    set_global_assignment -name SAVE_DISK_SPACE OFF
    set_global_assignment -name SMART_RECOMPILE ON
    set_global_assignment -name QII_AUTO_PACKED_REGISTERS AUTO
    set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
    set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
    set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ON
    set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE PARALLEL X8"
    set_global_assignment -name GENERATE_RBF_FILE ON
    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
    set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
    set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
    set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
    set_global_assignment -name ALLOW_REGISTER_MERGING ON
    set_global_assignment -name ENABLE_OCT_DONE OFF
    set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
    set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
    set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
    set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
    set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    set_global_assignment -name SYSTEMVERILOG_FILE pin_pgm_original.sv
    set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to resn_pin
    
    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
    
    Note the lines beginning with"//" are not used as these pins do not exist in theA9 version.

    In the A2 version I noted that the LEDs appeared to be backwards (led0 <--> led7) ???

    I will post the pinout pic shortly.
  • Cluso99 wrote: »
    Chip,
    Here is the BeMicroCV-A9.qsf file.
    set_global_assignment -name DEVICE 5CEFA9F23C8N
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name TOP_LEVEL_ENTITY top
    set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2"
    set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:54  OCTOBER 05, 2012"
    set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
    set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
    
    set_location_assignment PIN_H13 -to clock_50
    
    set_location_assignment PIN_D21 -to led[7]
    set_location_assignment PIN_D19 -to led[6]
    set_location_assignment PIN_C21 -to led[5]
    set_location_assignment PIN_C20 -to led[4]
    set_location_assignment PIN_B21 -to led[3]
    set_location_assignment PIN_E21 -to led[2]
    set_location_assignment PIN_E19 -to led[1]
    set_location_assignment PIN_B17 -to led[0]
    
    set_location_assignment PIN_C16 -to dip_sw[1]
    set_location_assignment PIN_D17 -to dip_sw[2]
    set_location_assignment PIN_G17 -to dip_sw[3]
    
    set_location_assignment PIN_H18 -to s[1]
    set_location_assignment PIN_J18 -to s[2]
    
    # j4 pins
    //set_location_assignment PIN_G1 -to p[36]
    //set_location_assignment PIN_G2 -to p[37]
    set_location_assignment PIN_V10 -to p[38]
    set_location_assignment PIN_P8 -to p[39]
    set_location_assignment PIN_R7 -to p[40]
    set_location_assignment PIN_P7 -to p[41]
    set_location_assignment PIN_W8 -to p[42]
    //set_location_assignment PIN_W9 -to p[43]
    //set_location_assignment PIN_U6 -to p[44]
    //set_location_assignment PIN_V6 -to p[45]
    //set_location_assignment PIN_U7 -to p[46]
    //set_location_assignment PIN_U8 -to p[47]
    //set_location_assignment PIN_AA7 -to p[48]
    //set_location_assignment PIN_AB7 -to p[49]
    //set_location_assignment PIN_AB6 -to p[50]
    //set_location_assignment PIN_AB5 -to p[51]
    //set_location_assignment PIN_AA8 -to p[52]
    //set_location_assignment PIN_AB8 -to p[53]
    set_location_assignment PIN_AA10 -to p[58]
    //set_location_assignment PIN_AA9 -to p[54]
    set_location_assignment PIN_Y10 -to p[59]
    set_location_assignment PIN_Y9 -to p[60]
    
    set_location_assignment PIN_R12 -to resn_pin
    set_location_assignment PIN_P12 -to p[61]
    set_location_assignment PIN_AB10 -to p[63]
    set_location_assignment PIN_AB11 -to p[62]
    //set_location_assignment PIN_Y11 -to p[55]
    //set_location_assignment PIN_AA12 -to p[56]
    
    # j1 pins
    set_location_assignment PIN_R11 -to p[0]
    set_location_assignment PIN_R10 -to p[1]
    set_location_assignment PIN_U12 -to p[2]
    set_location_assignment PIN_U11 -to p[3]
    set_location_assignment PIN_R9 -to p[4]
    set_location_assignment PIN_T10 -to p[5]
    set_location_assignment PIN_U10 -to p[6]
    set_location_assignment PIN_T9 -to p[7]
    set_location_assignment PIN_N16 -to p[8]
    set_location_assignment PIN_M16 -to p[9]
    set_location_assignment PIN_N19 -to p[10]
    set_location_assignment PIN_M18 -to p[11]
    set_location_assignment PIN_K17 -to p[12]
    set_location_assignment PIN_L17 -to p[13]
    set_location_assignment PIN_L19 -to p[14]
    set_location_assignment PIN_L18 -to p[15]
    set_location_assignment PIN_T18 -to p[16]
    set_location_assignment PIN_T17 -to p[17]
    //set_location_assignment PIN_T19 -to p[33]
    //set_location_assignment PIN_T20 -to p[35]
    set_location_assignment PIN_Y11 -to p[18]
    set_location_assignment PIN_AA12 -to p[19]
    set_location_assignment PIN_AA8 -to p[20]
    set_location_assignment PIN_AB8 -to p[21]
    set_location_assignment PIN_T19 -to p[22]
    set_location_assignment PIN_T20 -to p[23]
    set_location_assignment PIN_T22 -to p[24]
    set_location_assignment PIN_AA9 -to p[25]
    set_location_assignment PIN_P21 -to p[26]
    set_location_assignment PIN_R17 -to p[27]
    set_location_assignment PIN_R22 -to p[28]
    set_location_assignment PIN_R16 -to p[29]
    set_location_assignment PIN_P22 -to p[30]
    set_location_assignment PIN_R15 -to p[31]
    //set_location_assignment PIN_T22 -to p[34]
    set_location_assignment PIN_T15 -to p[32]
    
    # missing pin
    set_location_assignment PIN_L7 -to p[57]
    
    
    set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
    set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
    set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
    set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
    
    set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
    set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
    set_global_assignment -name SEED 1
    
    set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
    set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
    set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
    set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
    set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
    set_global_assignment -name FITTER_EFFORT "AUTO FIT"
    set_global_assignment -name SAVE_DISK_SPACE OFF
    set_global_assignment -name SMART_RECOMPILE ON
    set_global_assignment -name QII_AUTO_PACKED_REGISTERS AUTO
    set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
    set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
    set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ON
    set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE PARALLEL X8"
    set_global_assignment -name GENERATE_RBF_FILE ON
    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
    set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
    set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
    set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
    set_global_assignment -name ALLOW_REGISTER_MERGING ON
    set_global_assignment -name ENABLE_OCT_DONE OFF
    set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
    set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
    set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
    set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
    set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    set_global_assignment -name SYSTEMVERILOG_FILE pin_pgm_original.sv
    set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to resn_pin
    
    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
    
    Note the lines beginning with"//" are not used as these pins do not exist in theA9 version.

    In the A2 version I noted that the LEDs appeared to be backwards (led0 <--> led7) ???

    I will post the pinout pic shortly.

    I don't understand something here. Those // pins that don't exist, actually do exist in the BeMicro CV A9 board document. What am I to do with those?
  • Here is the BeMicro CV-A9 Layout
    BeMicroCV-A9%20P2%20Layout.png
    696 x 928 - 581K
  • cgracey wrote: »
    Cluso99 wrote: »
    Chip,
    Here is the BeMicroCV-A9.qsf file.
    set_global_assignment -name DEVICE 5CEFA9F23C8N
    set_global_assignment -name FAMILY "Cyclone V"
    set_global_assignment -name TOP_LEVEL_ENTITY top
    set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2"
    set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:54  OCTOBER 05, 2012"
    set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
    set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
    
    set_location_assignment PIN_H13 -to clock_50
    
    set_location_assignment PIN_D21 -to led[7]
    set_location_assignment PIN_D19 -to led[6]
    set_location_assignment PIN_C21 -to led[5]
    set_location_assignment PIN_C20 -to led[4]
    set_location_assignment PIN_B21 -to led[3]
    set_location_assignment PIN_E21 -to led[2]
    set_location_assignment PIN_E19 -to led[1]
    set_location_assignment PIN_B17 -to led[0]
    
    set_location_assignment PIN_C16 -to dip_sw[1]
    set_location_assignment PIN_D17 -to dip_sw[2]
    set_location_assignment PIN_G17 -to dip_sw[3]
    
    set_location_assignment PIN_H18 -to s[1]
    set_location_assignment PIN_J18 -to s[2]
    
    # j4 pins
    //set_location_assignment PIN_G1 -to p[36]
    //set_location_assignment PIN_G2 -to p[37]
    set_location_assignment PIN_V10 -to p[38]
    set_location_assignment PIN_P8 -to p[39]
    set_location_assignment PIN_R7 -to p[40]
    set_location_assignment PIN_P7 -to p[41]
    set_location_assignment PIN_W8 -to p[42]
    //set_location_assignment PIN_W9 -to p[43]
    //set_location_assignment PIN_U6 -to p[44]
    //set_location_assignment PIN_V6 -to p[45]
    //set_location_assignment PIN_U7 -to p[46]
    //set_location_assignment PIN_U8 -to p[47]
    //set_location_assignment PIN_AA7 -to p[48]
    //set_location_assignment PIN_AB7 -to p[49]
    //set_location_assignment PIN_AB6 -to p[50]
    //set_location_assignment PIN_AB5 -to p[51]
    //set_location_assignment PIN_AA8 -to p[52]
    //set_location_assignment PIN_AB8 -to p[53]
    set_location_assignment PIN_AA10 -to p[58]
    //set_location_assignment PIN_AA9 -to p[54]
    set_location_assignment PIN_Y10 -to p[59]
    set_location_assignment PIN_Y9 -to p[60]
    
    set_location_assignment PIN_R12 -to resn_pin
    set_location_assignment PIN_P12 -to p[61]
    set_location_assignment PIN_AB10 -to p[63]
    set_location_assignment PIN_AB11 -to p[62]
    //set_location_assignment PIN_Y11 -to p[55]
    //set_location_assignment PIN_AA12 -to p[56]
    
    # j1 pins
    set_location_assignment PIN_R11 -to p[0]
    set_location_assignment PIN_R10 -to p[1]
    set_location_assignment PIN_U12 -to p[2]
    set_location_assignment PIN_U11 -to p[3]
    set_location_assignment PIN_R9 -to p[4]
    set_location_assignment PIN_T10 -to p[5]
    set_location_assignment PIN_U10 -to p[6]
    set_location_assignment PIN_T9 -to p[7]
    set_location_assignment PIN_N16 -to p[8]
    set_location_assignment PIN_M16 -to p[9]
    set_location_assignment PIN_N19 -to p[10]
    set_location_assignment PIN_M18 -to p[11]
    set_location_assignment PIN_K17 -to p[12]
    set_location_assignment PIN_L17 -to p[13]
    set_location_assignment PIN_L19 -to p[14]
    set_location_assignment PIN_L18 -to p[15]
    set_location_assignment PIN_T18 -to p[16]
    set_location_assignment PIN_T17 -to p[17]
    //set_location_assignment PIN_T19 -to p[33]
    //set_location_assignment PIN_T20 -to p[35]
    set_location_assignment PIN_Y11 -to p[18]
    set_location_assignment PIN_AA12 -to p[19]
    set_location_assignment PIN_AA8 -to p[20]
    set_location_assignment PIN_AB8 -to p[21]
    set_location_assignment PIN_T19 -to p[22]
    set_location_assignment PIN_T20 -to p[23]
    set_location_assignment PIN_T22 -to p[24]
    set_location_assignment PIN_AA9 -to p[25]
    set_location_assignment PIN_P21 -to p[26]
    set_location_assignment PIN_R17 -to p[27]
    set_location_assignment PIN_R22 -to p[28]
    set_location_assignment PIN_R16 -to p[29]
    set_location_assignment PIN_P22 -to p[30]
    set_location_assignment PIN_R15 -to p[31]
    //set_location_assignment PIN_T22 -to p[34]
    set_location_assignment PIN_T15 -to p[32]
    
    # missing pin
    set_location_assignment PIN_L7 -to p[57]
    
    
    set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
    set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
    set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
    set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
    set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
    
    set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
    set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
    set_global_assignment -name SEED 1
    
    set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
    set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
    set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
    set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
    set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
    set_global_assignment -name FITTER_EFFORT "AUTO FIT"
    set_global_assignment -name SAVE_DISK_SPACE OFF
    set_global_assignment -name SMART_RECOMPILE ON
    set_global_assignment -name QII_AUTO_PACKED_REGISTERS AUTO
    set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
    set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
    set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
    set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ON
    set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE PARALLEL X8"
    set_global_assignment -name GENERATE_RBF_FILE ON
    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
    set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
    set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
    set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
    set_global_assignment -name ALLOW_REGISTER_MERGING ON
    set_global_assignment -name ENABLE_OCT_DONE OFF
    set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
    set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
    set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
    set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
    set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    set_global_assignment -name SYSTEMVERILOG_FILE pin_pgm_original.sv
    set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to resn_pin
    
    set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
    
    Note the lines beginning with"//" are not used as these pins do not exist in theA9 version.

    In the A2 version I noted that the LEDs appeared to be backwards (led0 <--> led7) ???

    I will post the pinout pic shortly.

    I don't understand something here. Those // pins that don't exist, actually do exist in the BeMicro CV A9 board document. What am I to do with those?
    According to the BeMicro CV A9 FPGA Development Board Hardware Reference Guide, those pins are not connected to the 40 pin connectors J1 & J4. Therefore, these lines need to be deleted from the qsf file. I did not do this in case you need to specify the Pxx pins that are no longer referenced.

    The A9 chip has a number of I/O pins that are changed to VCCINT from the A2 version. I presume these are some of those pins.

    Hope this makes sense.
  • cgraceycgracey Posts: 12,800
    edited 2016-06-16 - 10:55:07
    *** THIS PINOUT HAS BEEN UPDATED FROM THE ORIGINAL POST TO ACCOMMODATE THE MICRO SD SLOT ***


    Cluso99,

    I made a different pinout while I was waiting for word back from you, after I noticed the PropPlug pins needed a wire jumper. It's compiling right now and will probably need to run for a few hours.

    Meanwhile, could you please send me a straight-from-above overhead shot of that A9 board? I have that paint.net program and it will let me align the text to the pins perfectly via fractional point sizes on the font.

    Here is the pinout now (odd pin #'s shown on left):
    J1 - right
    
    1		(nc)			T15	p[60]
    3		P22	p[59]		R15	p[61]
    5		R22	p[58]		R16	p[62]
    7		R21	p[57]		R17	p[63]
    9		T22	p[56]		AA9	resn_pin
    11		(5v)			(gnd)	GND
    13		T19	p[22]		T20	p[23]
    15		AA8	p[20]		AB8	p[21]
    17		Y11	p[18]		AA12	p[19]
    19		(nc)			(nc)
    21		T18	p[16]		T17	p[17]
    23		L19	p[14]		L18	p[15]
    25		K17	p[12]		L17	p[13]
    27		N19	p[10]		M18	p[11]
    29		(3.3v)			(gnd)
    31		N16	p[8]		M16	p[9]
    33		U10	p[6]		T9	p[7]
    35		R9	p[4]		T10	p[5]
    37		U12	p[2]		U11	p[3]
    39		R11	p[0]		R10	p[1]
    
    
    J4 - left
    
    1		(3.3v)			(3.3v)
    3		(nc)			(nc)
    5		V10	p[34]		P8	p[35]
    7		(gnd)			(gnd)
    9		(gnd)			(gnd)
    11		R7	p[32]		P7	p[33]
    13		W8	p[31]		(nc)
    15		(nc)			(nc)
    17		(gnd)			(gnd)
    19		(nc)			(nc)
    21		(nc)			(nc)
    23		(nc)			(nc)
    25		(gnd)			(gnd)
    27		(nc)			(nc)
    29		AA10	p[30]		(nc)
    31		Y10	p[28]		Y9	p[29]
    33		(gnd)			(gnd)
    35		R12	p[26]		P12	p[27]
    37		AB10	p[24]		AB11	p[25]
    39		(nc)			(nc)
    
    
    J2 - edge connector
    
    3		U13	p[42]
    5		W16	p[43]
    7		V15	p[44]
    9		AA13	p[45]
    11		AA14	p[46]
    13		Y14	p[47]
    15		AB15	p[48]
    17		AA15	p[49]
    19		Y15	p[50]	(input = dip switch 1)
    21		(gnd)
    23		Y16	p[51]	(input = dip switch 2)
    25		AB17	p[52]	(input = dip switch 3)
    27		AA17	p[53]	(input = dip switch 4)
    29		Y17	p[54]	(input = pushbutton 1)
    31		AB18	p[55]	(input = pushbutton 2)
    
    
    P1 - micro SD slot
    
    SDD0		U6	p[36]
    SDD1		V6	p[37]
    SDD2		U7	p[38]
    SDD3		U8	p[39]
    SDCMD		W9	p[40]
    SDCLK		M22	p[41]
    
    
    Eight LEDs indicate cogs 0..7 active
    
  • jmgjmg Posts: 14,324
    In regards to the CV-A9, if we can boot off the microSD then we needn't worry about SPI Flash if that makes it easier. What was decided about booting off SD? Something simple I hope, like just booting from sector 0 etc.

    IIRC one issue around SD boot, was reset handling - ie Power up boot, is more predictable than a software reset or watchdog reboot, as you can be in another mode.
    Even QuadSPI parts will need extra pins defined during SPI BOOT, to ensure HOLD# and WP# are held in valid states. Call thus QuadSPI safe.
    Also, with no reset pin, a QuadSPI-safe boot should send a part an exit-quad mode, just in case reset occurred when in Quad mode. Hopefully, single SPI parts just ignore that.


  • jmg wrote: »
    In regards to the CV-A9, if we can boot off the microSD then we needn't worry about SPI Flash if that makes it easier. What was decided about booting off SD? Something simple I hope, like just booting from sector 0 etc.

    IIRC one issue around SD boot, was reset handling - ie Power up boot, is more predictable than a software reset or watchdog reboot, as you can be in another mode.
    Even QuadSPI parts will need extra pins defined during SPI BOOT, to ensure HOLD# and WP# are held in valid states. Call thus QuadSPI safe.
    Also, with no reset pin, a QuadSPI-safe boot should send a part an exit-quad mode, just in case reset occurred when in Quad mode. Hopefully, single SPI parts just ignore that.


    Nothing has been decided about SD boot. It's still a hugely debatable matter, as to HOW to do it.

    I could change the BeMicro A9 pinout to accommodate that SD slot... I just changed the BeMicro A9 pinout and I am recompiling now. I updated the BeMicro A9 pinout above to reflect the changes. So, this A9 board will be able to exercise its Micro SD slot, in case anyone wants to get it working.
  • Peter JakackiPeter Jakacki Posts: 9,096
    edited 2016-06-16 - 10:59:49
    cgracey wrote: »

    Nothing has been decided about SD boot. It's still a hugely debatable matter, as to HOW to do it.

    I could change the BeMicro A9 pinout to accommodate that SD slot... I just changed the BeMicro A9 pinout and I am recompiling now. I updated the BeMicro A9 pinout above to reflect the changes. So, this A9 board will be able to exercise its Micro SD slot, in case anyone wants to get it working.

    The HOW TO should be KISS, even if it is simply to get us off the ground and running as if we lifted ourselves up by our own bootstraps :) (hint: sector zero)
    I can easily bring up FAT32 and SD code on my Tachyon system to test it but the whole idea of having boot memory is so I don't have to reload serially each time while I test it :)

    Now Chip, I know this first hand too but isn't it time for either breakfast or bed?

  • Chip
    Loaded all 5 variants of V10 onto appropriate P123-A9,DE2-115,DE0-Nano,DE0-Nano + add_on and BeMicro CV-A2 boards.
    All varaints appear to be working Ok. :)

    P.S. I can test BeMicro CV-A9 too when your compile finishes.
  • BeMicro CV A9 board picture
    BeMicro-CV-A9-pcb.JPG
    1632 x 1224 - 498K
  • cgracey wrote: »
    *** THIS PINOUT HAS BEEN UPDATED FROM THE ORIGINAL POST TO ACCOMMODATE THE MICRO SD SLOT ***


    Cluso99,

    I made a different pinout while I was waiting for word back from you, after I noticed the PropPlug pins needed a wire jumper. It's compiling right now and will probably need to run for a few hours.

    Meanwhile, could you please send me a straight-from-above overhead shot of that A9 board? I have that paint.net program and it will let me align the text to the pins perfectly via fractional point sizes on the font.

    Here is the pinout now (odd pin #'s shown on left):
    J1 - right
    
    1		(nc)			T15	p[60]
    3		P22	p[59]		R15	p[61]
    5		R22	p[58]		R16	p[62]
    7		R21	p[57]		R17	p[63]
    9		T22	p[56]		AA9	resn_pin
    11		(5v)			(gnd)	GND
    13		T19	p[22]		T20	p[23]
    15		AA8	p[20]		AB8	p[21]
    17		Y11	p[18]		AA12	p[19]
    19		(nc)			(nc)
    21		T18	p[16]		T17	p[17]
    23		L19	p[14]		L18	p[15]
    25		K17	p[12]		L17	p[13]
    27		N19	p[10]		M18	p[11]
    29		(3.3v)			(gnd)
    31		N16	p[8]		M16	p[9]
    33		U10	p[6]		T9	p[7]
    35		R9	p[4]		T10	p[5]
    37		U12	p[2]		U11	p[3]
    39		R11	p[0]		R10	p[1]
    
    
    J4 - left
    
    1		(3.3v)			(3.3v)
    3		(nc)			(nc)
    5		V10	p[34]		P8	p[35]
    7		(gnd)			(gnd)
    9		(gnd)			(gnd)
    11		R7	p[32]		P7	p[33]
    13		W8	p[31]		(nc)
    15		(nc)			(nc)
    17		(gnd)			(gnd)
    19		(nc)			(nc)
    21		(nc)			(nc)
    23		(nc)			(nc)
    25		(gnd)			(gnd)
    27		(nc)			(nc)
    29		AA10	p[30]		(nc)
    31		Y10	p[28]		Y9	p[29]
    33		(gnd)			(gnd)
    35		R12	p[26]		P12	p[27]
    37		AB10	p[24]		AB11	p[25]
    39		(nc)			(nc)
    
    
    J2 - edge connector
    
    3		U13	p[42]
    5		W16	p[43]
    7		V15	p[44]
    9		AA13	p[45]
    11		AA14	p[46]
    13		Y14	p[47]
    15		AB15	p[48]
    17		AA15	p[49]
    19		Y15	p[50]	(input = dip switch 1)
    21		(gnd)
    23		Y16	p[51]	(input = dip switch 2)
    25		AB17	p[52]	(input = dip switch 3)
    27		AA17	p[53]	(input = dip switch 4)
    29		Y17	p[54]	(input = pushbutton 1)
    31		AB18	p[55]	(input = pushbutton 2)
    
    
    P1 - micro SD slot
    
    SDD0		U6	p[36]
    SDD1		V6	p[37]
    SDD2		U7	p[38]
    SDD3		U8	p[39]
    SDCMD		W9	p[40]
    SDCLK		M22	p[41]
    
    
    Eight LEDs indicate cogs 0..7 active
    
    Excellent work Chip.
    Looking forward to trying SD too but I will have to convert Kye's FAT driver first.

  • Cluso99 wrote: »
    BeMicro CV A9 board picture
    BeMicro-CV-A9-pcb.JPG

    Would you mind taking one more where you get further away, and then zoom in. This will make things telescopic, so that pins won't be at much of an angle. I think you need to have the camera/phone at least two feet above the board, zoomed in. The rotational angle is not critical, but it should be flat-on.
  • For the smaller FPGAs, since they are already resource-constrained, would it make more sense to restrict their feature set to more closely match the smaller ASIC variants that Chip told us about? For instance, if there is going to be an 8-cog, 32-pin version, why not make the DE0 Nano (etc) 32-pin only. That way, Chip can make sure that there aren't any edge cases that need to be taken into account up front (e.g. booting off pins 31..30, instead of pins 63..62).

    (Actually, it might also do to make restricted variants for the A9, as well. This would allow A9 owners to test the same code across multiple variations, which would be similar to the approach many have suggested for the ASIC: design on the large version, run on a smaller version.)
  • cgracey wrote: »

    Nothing has been decided about SD boot. It's still a hugely debatable matter, as to HOW to do it.

    I could change the BeMicro A9 pinout to accommodate that SD slot... I just changed the BeMicro A9 pinout and I am recompiling now. I updated the BeMicro A9 pinout above to reflect the changes. So, this A9 board will be able to exercise its Micro SD slot, in case anyone wants to get it working.

    The HOW TO should be KISS, even if it is simply to get us off the ground and running as if we lifted ourselves up by our own bootstraps :) (hint: sector zero)
    I can easily bring up FAT32 and SD code on my Tachyon system to test it but the whole idea of having boot memory is so I don't have to reload serially each time while I test it :)

    Now Chip, I know this first hand too but isn't it time for either breakfast or bed?


    It's time for bed. I don't trust my brain when it's tired, anymore. I've just been babysitting this compile, in case something goes wrong. It looks like it's going to finish okay, though.
  • ozpropdev wrote: »
    Chip
    Loaded all 5 variants of V10 onto appropriate P123-A9,DE2-115,DE0-Nano,DE0-Nano + add_on and BeMicro CV-A2 boards.
    All varaints appear to be working Ok. :)

    P.S. I can test BeMicro CV-A9 too when your compile finishes.

    Thanks for checking all those.
  • Is this suitable?
    BeMicro_CV_A9_board.JPG
    3264 x 2448 - 895K
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