Prop2 FPGA files!!! - Updated 1 January 2018 - Version 31

1112113114115117

Comments

  • I think I've got the documentation all up-to-date, including all CLKSET functions and the timeout modes in the smart pins.

    Next, I'll put the instruction set to bed for, hopefully, the last time by pushing out the latest internal Verilog into v31.

    After that, I have a lot of communicating to do with OnSemi.

    And after that, I want to get back to Spin2.

    ErNa wrote: »
    What about TachyonRealtimeUniversalMulticoreProcessor? Would look as if sun rises from the west, seen from good old europe?

    That's a great idea. Do you think we could make it shorter, though? That's way better than MulticoreEnhancedRealtimeKelvinEscalatingLaptop.
  • TonyB_, here is the pending v31 instruction map. I think you might have already seen this:

    https://docs.google.com/spreadsheets/d/12GWGrEmp72MUIBvoXWadjWwqngrgQRqh9eYq6XhpEYQ/edit?usp=sharing
  • TonyB_TonyB_ Posts: 293
    edited December 2017 Vote Up0Vote Down
    cgracey wrote: »
    TonyB_, here is the pending v31 instruction map. I think you might have already seen this:

    https://docs.google.com/spreadsheets/d/12GWGrEmp72MUIBvoXWadjWwqngrgQRqh9eYq6XhpEYQ/edit?usp=sharing

    Thanks, Chip. Here are my final comments on the instruction set. Most suggestions are new, the others repeated for completeness. My thinking is that if one instruction must move, the set will have changed and might as well move some others and have done with it. Numbering is by ascending opcodes, not importance.

    * = instruction moved or changed

    1. TEST and others

    Move as shown below, so that all three instructions that use S/!S, namely AND/ANDN and MOV/NOT and TEST/TESTN, have opcode bits [23:21] = 000/001, making the coding more consistent and harmonious.

    Before:
    EEEE 0111000 CZI DDDDDDDDD SSSSSSSSS        INCMOD  D,S/#       {WC/WZ/WCZ}
    EEEE 0111001 CZI DDDDDDDDD SSSSSSSSS        DECMOD  D,S/#       {WC/WZ/WCZ}
    EEEE 0111010 CZI DDDDDDDDD SSSSSSSSS        ZEROX   D,S/#       {WC/WZ/WCZ}
    EEEE 0111011 CZI DDDDDDDDD SSSSSSSSS        SIGNX   D,S/#       {WC/WZ/WCZ}
    
    EEEE 0111100 CZI DDDDDDDDD SSSSSSSSS        ENCOD   D,S/#       {WC/WZ/WCZ}
    EEEE 0111101 CZI DDDDDDDDD SSSSSSSSS        ONES    D,S/#       {WC/WZ/WCZ}
    EEEE 0111110 CZI DDDDDDDDD SSSSSSSSS        TEST    D,S/#       {WC/WZ/WCZ}
    EEEE 0111111 CZI DDDDDDDDD SSSSSSSSS        TESTN   D,S/#       {WC/WZ/WCZ}
    
    After:
    EEEE 0111000 CZI DDDDDDDDD SSSSSSSSS    *   TEST    D,S/#       {WC/WZ/WCZ}
    EEEE 0111001 CZI DDDDDDDDD SSSSSSSSS    *   TESTN   D,S/#       {WC/WZ/WCZ}
    EEEE 0111010 CZI DDDDDDDDD SSSSSSSSS    *   ENCOD   D,S/#       {WC/WZ/WCZ}
    EEEE 0111011 CZI DDDDDDDDD SSSSSSSSS    *   ONES    D,S/#       {WC/WZ/WCZ}
    
    EEEE 0111100 CZI DDDDDDDDD SSSSSSSSS    *   INCMOD  D,S/#       {WC/WZ/WCZ}
    EEEE 0111101 CZI DDDDDDDDD SSSSSSSSS    *   DECMOD  D,S/#       {WC/WZ/WCZ}
    EEEE 0111110 CZI DDDDDDDDD SSSSSSSSS    *   ZEROX   D,S/#       {WC/WZ/WCZ}
    EEEE 0111111 CZI DDDDDDDDD SSSSSSSSS    *   SIGNX   D,S/#       {WC/WZ/WCZ}
    

    2. RDFAST and others

    Move as shown, so that RDFAST/WRFAST opcodes differ by only one bit.

    Before:
    EEEE 1100011 1LI DDDDDDDDD SSSSSSSSS        RDFAST  D/#,S/#
    EEEE 1100100 0LI DDDDDDDDD SSSSSSSSS        WRFAST  D/#,S/#
    EEEE 1100100 1LI DDDDDDDDD SSSSSSSSS        FBLOCK  D/#,S/#
    
    After:
    EEEE 1100011 1LI DDDDDDDDD SSSSSSSSS    *   FBLOCK  D/#,S/#
    EEEE 1100100 0LI DDDDDDDDD SSSSSSSSS    *   RDFAST  D/#,S/#
    EEEE 1100100 1LI DDDDDDDDD SSSSSSSSS    *   WRFAST  D/#,S/#
    

    3. RFBYTE and others

    Move as shown, so that RFVAR/RFVARS, RFBYTE/WFBYTE, RFWORD/WFWORD and RFLONG/WFLONG differ by the same single bit.

    Before:
    EEEE 1101011 CZ0 DDDDDDDDD 000010000        RFBYTE  D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010001        RFWORD  D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010010        RFLONG  D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010011        RFVAR   D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010100        RFVARS  D           {WC/WZ/WCZ}
    
    EEEE 1101011 00L DDDDDDDDD 000010101        WFBYTE  D/#
    EEEE 1101011 00L DDDDDDDDD 000010110        WFWORD  D/#
    EEEE 1101011 00L DDDDDDDDD 000010111        WFLONG  D/#
    
    After:
    EEEE 1101011 CZ0 DDDDDDDDD 000010000    *   RFVAR   D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010001    *   RFBYTE  D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010010    *   RFWORD  D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010011    *   RFLONG  D           {WC/WZ/WCZ}
    EEEE 1101011 CZ0 DDDDDDDDD 000010100        RFVARS  D           {WC/WZ/WCZ}
    
    EEEE 1101011 00L DDDDDDDDD 000010101        WFBYTE  D/#
    EEEE 1101011 00L DDDDDDDDD 000010110        WFWORD  D/#
    EEEE 1101011 00L DDDDDDDDD 000010111        WFLONG  D/#
    

    4. MODCZ and others

    Does not involve D (nor S), so out of place in with the registered D instructions. I think it could be moved in front of POLLINT, with bit 17 changed from 0 to 1 for POLLxxx and WAITxxx.

    Before:
    EEEE 1101011 CZ0 000000000 000100100        POLLINT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000001 000100100        POLLCT1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000010 000100100        POLLCT2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000011 000100100        POLLCT3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000100 000100100        POLLSE1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000101 000100100        POLLSE2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000110 000100100        POLLSE3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000000111 000100100        POLLSE4             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001000 000100100        POLLPAT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001001 000100100        POLLFBW             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001010 000100100        POLLXMT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001011 000100100        POLLXFI             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001100 000100100        POLLXRO             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001101 000100100        POLLXRL             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001110 000100100        POLLATN             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000001111 000100100        POLLQMT             {WC/WZ/WCZ}
    
    EEEE 1101011 CZ0 000010000 000100100        WAITINT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010001 000100100        WAITCT1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010010 000100100        WAITCT2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010011 000100100        WAITCT3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010100 000100100        WAITSE1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010101 000100100        WAITSE2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010110 000100100        WAITSE3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000010111 000100100        WAITSE4             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011000 000100100        WAITPAT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011001 000100100        WAITFBW             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011010 000100100        WAITXMT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011011 000100100        WAITXFI             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011100 000100100        WAITXRO             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011101 000100100        WAITXRL             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 000011110 000100100        WAITATN             {WC/WZ/WCZ}
    
    EEEE 1101011 CZ1 0cccczzzz 001101111        MODCZ   c,z         {WC/WZ/WCZ}
    
    After:
    EEEE 1101011 CZ0 0cccczzzz 000100100    *   MODCZ   c,z         {WC/WZ/WCZ}
    
    EEEE 1101011 CZ0 100000000 000100100    *   POLLINT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000001 000100100    *   POLLCT1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000010 000100100    *   POLLCT2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000011 000100100    *   POLLCT3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000100 000100100    *   POLLSE1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000101 000100100    *   POLLSE2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000110 000100100    *   POLLSE3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100000111 000100100    *   POLLSE4             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001000 000100100    *   POLLPAT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001001 000100100    *   POLLFBW             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001010 000100100    *   POLLXMT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001011 000100100    *   POLLXFI             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001100 000100100    *   POLLXRO             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001101 000100100    *   POLLXRL             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001110 000100100    *   POLLATN             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100001111 000100100    *   POLLQMT             {WC/WZ/WCZ}
    
    EEEE 1101011 CZ0 100010000 000100100    *   WAITINT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010001 000100100    *   WAITCT1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010010 000100100    *   WAITCT2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010011 000100100    *   WAITCT3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010100 000100100    *   WAITSE1             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010101 000100100    *   WAITSE2             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010110 000100100    *   WAITSE3             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100010111 000100100    *   WAITSE4             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011000 000100100    *   WAITPAT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011001 000100100    *   WAITFBW             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011010 000100100    *   WAITXMT             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011011 000100100    *   WAITXFI             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011100 000100100    *   WAITXRO             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011101 000100100    *   WAITXRL             {WC/WZ/WCZ}
    EEEE 1101011 CZ0 100011110 000100100    *   WAITATN             {WC/WZ/WCZ}
    

    5. STALLI and others

    Move as shown so that TRGINTx/NIXINTx differ by same bit. Also, bit 17 changed from 0 to 1 due to MODCZ move.

    Before:
    EEEE 1101011 000 000100000 000100100        ALLOWI
    EEEE 1101011 000 000100001 000100100        STALLI
    
    EEEE 1101011 000 000100010 000100100        TRGINT1
    EEEE 1101011 000 000100011 000100100        TRGINT2
    EEEE 1101011 000 000100100 000100100        TRGINT3
    
    EEEE 1101011 000 000100101 000100100        NIXINT1
    EEEE 1101011 000 000100110 000100100        NIXINT2
    EEEE 1101011 000 000100111 000100100        NIXINT3
    
    After:
    EEEE 1101011 000 100100000 000100100    *   ALLOWI
    EEEE 1101011 000 100100001 000100100    *   TRGINT1
    EEEE 1101011 000 100100010 000100100    *   TRGINT2
    EEEE 1101011 000 100100011 000100100    *   TRGINT3
    
    EEEE 1101011 000 100100100 000100100    *   STALLI
    EEEE 1101011 000 100100101 000100100    *   NIXINT1
    EEEE 1101011 000 100100110 000100100    *   NIXINT2
    EEEE 1101011 000 100100111 000100100    *   NIXINT3
    

    6. MERGEB and another

    Possibly move as shown, so that SPLITx/MERGEx are split, not merged!

    Before:
    EEEE 1101011 000 DDDDDDDDD 001100000        SPLITB  D
    EEEE 1101011 000 DDDDDDDDD 001100001        MERGEB  D
    EEEE 1101011 000 DDDDDDDDD 001100010        SPLITW  D
    EEEE 1101011 000 DDDDDDDDD 001100011        MERGEW  D
    
    After:
    EEEE 1101011 000 DDDDDDDDD 001100000        SPLITB  D
    EEEE 1101011 000 DDDDDDDDD 001100001    *   SPLITW  D
    EEEE 1101011 000 DDDDDDDDD 001100010    *   MERGEB  D
    EEEE 1101011 000 DDDDDDDDD 001100011        MERGEW  D
    

    Modified instructions.txt with above changes attached.

    Whether or not any of the above are implemented, that's me finished with the instruction set! :)

    Formerly known as TonyB
  • cgraceycgracey Posts: 8,538
    edited December 2017 Vote Up0Vote Down
    TonyB_, think in terms of what looks most sensible to programmers and tool makers. At this point, there are no huge gains to be gotten by simplifying decoding, as things are already compartmentalized behind the scenes. How it flows in peoples' minds is more important.
  • Let's avoid names like PropellerOnlineLicencedInternetTechnologyIntegratedComputerSystem. TAQOZ is fine.
  • ErNaErNa Posts: 1,027
    edited December 2017 Vote Up0Vote Down
    But what if avoiding names is promoting them? Maybe we should "beepbeepbeep" the word "Propeller" to make it the best known word in the world? What if HP outside the (electro-) technical world is expanded in the sense of PLATO
  • proplem wrote: »
    Happy new year !
    I'm using - no I'm enjoying - tachyon with P1 and one thing I'm definitely missing is flow control. Although Peter stated above that there currently is no fiddling with newline delay and character delay on the P2, I'm sure in future there will be.
    From my point of view the lack of flow control would avoid unmanned builds which is inconvenient in times of robots ...
    Best regards,
    proplem

    I also use FL fast load once I have EASYFILE loaded so that everything is buffered into a temporary or named file and loaded from the file where it is not necessary for flow control. With TAQOZ in P2 ROM this should be possible since I have FAT32 already resident, all it needs is an SD card. One advantage of downloading to a named file is that it is also an easy way to transfer source code onto the card. Maybe some of the newer USB serial chips have proper flow control built into them because as we know you can't rely upon the O/S to do it.
    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    Tachyon Forth News Blog
    TACHYON DEMONSTRATOR
    Brisbane, Australia
  • cgracey wrote: »
    I think I've got the documentation all up-to-date, including all CLKSET functions and the timeout modes in the smart pins.
    Chip,
    Changing the encoding of the selector bits to be at LSbit end will allow for the reset and write protect functions to be encoded as single instructions.
    Eg:
    CLKSET  D/#     - Configure global circuit selected by MSBs
    %DDDD_DDMM_MMMM_MMMM_PPPP_CCSS_Exxx_xx10      Set clock generator mode
    %0000_0000_0000_0000_0000_0001_0000_0000      Hard reset, reboots chip
    %0000_0000_0000_0000_0000_000P_1000_0000      Set write-protect of last 16KB RAM to P
    %0000_0000_0000_0000_RRLL_TTTT_T100_0000      Set filter R to length L and tap T
    %DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDD1      Seed Xoroshiro128+ PRNG with D
    
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • Actually, the immediate bit in the opcode could be exclusively for those two functions. In effect making them separate instructions.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    cgracey wrote: »
    I think I've got the documentation all up-to-date, including all CLKSET functions and the timeout modes in the smart pins.
    Chip,
    Changing the encoding of the selector bits to be at LSbit end will allow for the reset and write protect functions to be encoded as single instructions.
    Eg:
    CLKSET  D/#     - Configure global circuit selected by MSBs
    %DDDD_DDMM_MMMM_MMMM_PPPP_CCSS_Exxx_xx10      Set clock generator mode
    %0000_0000_0000_0000_0000_0001_0000_0000      Hard reset, reboots chip
    %0000_0000_0000_0000_0000_000P_1000_0000      Set write-protect of last 16KB RAM to P
    %0000_0000_0000_0000_RRLL_TTTT_T100_0000      Set filter R to length L and tap T
    %DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDD1      Seed Xoroshiro128+ PRNG with D
    

    What I don't like about that is that it makes setting the clock require ## for most cases. I think setting the clock is going to be the most common use of this instruction, so it needs to be the simplest.

    Here is how I see the the use cases in order of descending frequency:

    1) setting the clock (most common, as apps need to save power)
    2) write-protecting the last 16KB of RAM (used once/twice? by OS-type software)
    3) setting the filters (probably a one-time thing)
    4) resetting the chip (this has got to be rare)
    5) seeding the PRNG (done by boot ROM, no need after)

    It would be nice to be able to set 160MHz PLL operation from a 20MHz crystal. That would require something like this:

    %P_PPPD_DDDD_DMMM_MMMM_MMME_CCSS

    CLKSET #%1111_1_10_11

    That seems kind of messy, though, as it reorders the PLL config fields in a way that doesn't flow logically from left to right.

    The way it is now is maybe fine, considering the alternatives.
  • cgracey wrote: »
    It would be nice to be able to set 160MHz PLL operation from a 20MHz crystal. That would require something like this:

    %P_PPPD_DDDD_DMMM_MMMM_MMME_CCSS

    CLKSET #%1111_1_10_11

    That seems kind of messy, though, as it reorders the PLL config fields in a way that doesn't flow logically from left to right.

    The way it is now is maybe fine, considering the alternatives.
    I've noticed E field can be derived from CC field. How about splitting up the PLL config from the clock selection:
    CLKSET  D/#     - Configure global circuit selected by MSBs
    
    %0000_0000_PPPP_DDDD_DDMM_MMMM_MMMM_CC10      Config clock PLL generator
    %0000_0000_0000_0000_0000_0000_SS10_0000      Select clock source
    %0000_0000_0000_0000_0000_0001_0000_0000      Hard reset, reboots chip
    %0000_0000_0000_0000_0000_000P_1000_0000      Set write-protect of last 16KB RAM to P
    %0000_0000_0000_0000_RRLL_TTTT_T100_0000      Set filter R to length L and tap T
    %DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDD1      Seed Xoroshiro128+ PRNG with D
    

    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    cgracey wrote: »
    It would be nice to be able to set 160MHz PLL operation from a 20MHz crystal. That would require something like this:

    %P_PPPD_DDDD_DMMM_MMMM_MMME_CCSS

    CLKSET #%1111_1_10_11

    That seems kind of messy, though, as it reorders the PLL config fields in a way that doesn't flow logically from left to right.

    The way it is now is maybe fine, considering the alternatives.
    I've noticed E field can be derived from CC field. How about splitting up the PLL config from the clock selection:
    CLKSET  D/#     - Configure global circuit selected by MSBs
    
    %0000_0000_PPPP_DDDD_DDMM_MMMM_MMMM_CC10      Config clock PLL generator
    %0000_0000_0000_0000_0000_0000_SS10_0000      Select clock source
    %0000_0000_0000_0000_0000_0001_0000_0000      Hard reset, reboots chip
    %0000_0000_0000_0000_0000_000P_1000_0000      Set write-protect of last 16KB RAM to P
    %0000_0000_0000_0000_RRLL_TTTT_T100_0000      Set filter R to length L and tap T
    %DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDDD_DDD1      Seed Xoroshiro128+ PRNG with D
    

    But, what if you wanted the crystal oscillator running, but not the PLL, too? It takes extra power to run the PLL.
  • evanhevanh Posts: 4,489
    edited January 2 Vote Up0Vote Down
    Hmm ... hadn't thought of that option. The E field can be put where you suggested at bit4. I can't say I saw any flow issues.

    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    Hmm ... hadn't thought of that option. The E field can be put where you suggested at bit4. I can't say I saw any flow issues.

    I'm going to keep it how I've currently got it. I'm part way through compiling FPGA images now, and I don't want to start over. It's of marginal worth, either way. I think what we have now is simplest.
  • jmgjmg Posts: 10,760
    cgracey wrote: »
    But, what if you wanted the crystal oscillator running, but not the PLL, too? It takes extra power to run the PLL.

    If you wanted a CMOS clock source, and no Xtal amplifier, that seems to be missing ?
    Select of %CC=%01 is close, but has a signal on XO that is not strictly needed.
    The closest to 'Halt and wait for reset' looks to be 20kHz Osc select ?
  • jmg wrote: »
    cgracey wrote: »
    But, what if you wanted the crystal oscillator running, but not the PLL, too? It takes extra power to run the PLL.

    If you wanted a CMOS clock source, and no Xtal amplifier, that seems to be missing ?
    Select of %CC=%01 is close, but has a signal on XO that is not strictly needed.
    The closest to 'Halt and wait for reset' looks to be 20kHz Osc select ?

    If you drive a signal into XI, XO will output the opposite with CC=%01. There will be no loading caps. I figured the clock-input mode %01 could follow on XO to allow some custom C-loading for a lower-C crystal.

    Yes. 20KHz would draw way less power than the quiescent leakage. That is the power-down mode.
  • cgracey wrote: »
    I'm going to keep it how I've currently got it. I'm part way through compiling FPGA images now, and I don't want to start over. It's of marginal worth, either way. I think what we have now is simplest.
    If you do revisit it then turning it into four separate instructions also seems sensible. One for the random seed, one for xtal/pll config, one for pin filters, and one for clock-select and reset and write-protect.

    That would provide maximal immediate addressing and, being single operand, they don't consume any valuable encoding space.

    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • I posted the new v31 at the top of this thread.

    WHAT's NEW:

    * Streamer pins now wrap around for 16-and 32-bit data paths on upper 8-pin offsets
    * AND/ANDN, TEST/TESTN, and SETPIV/SETPIX have swapped encodings
    * SCLU/SCL have been renamed to SCA/SCAS
    * CLKSET has been renamed to HUBSET
    * New MODC/MODZ aliases for MODCZ

    This is the latest (and I think darn-near final) Verilog. This is in OnSemi's hands now and they are developing their compilation scripts with it.

    Please try it out, if you can.

    Thanks!
  • WIll do very soon!
    Cheers
    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    Tachyon Forth News Blog
    TACHYON DEMONSTRATOR
    Brisbane, Australia
  • jmgjmg Posts: 10,760
    cgracey wrote: »
    .... This is in OnSemi's hands now and they are developing their compilation scripts with it.

    Now that sounds a lot like a milestone !! :)

  • I also use FL fast load once I have EASYFILE loaded so that everything is buffered into a temporary or named file and loaded from the file where it is not necessary for flow control. With TAQOZ in P2 ROM this should be possible since I have FAT32 already resident, all it needs is an SD card. One advantage of downloading to a named file is that it is also an easy way to transfer source code onto the card. Maybe some of the newer USB serial chips have proper flow control built into them because as we know you can't rely upon the O/S to do it.
    @Peter,
    is this FL something like redirecting serial in into a temporary file on sdcard and then loading from that file so that compilarion/execution is delayed but save?

    Maybe you can answer in the tachyon thread to keep others informed about this. Thanks!
    I Am One With the Forth and the Forth Is With Me
  • proplem wrote: »
    I also use FL fast load once I have EASYFILE loaded so that everything is buffered into a temporary or named file and loaded from the file where it is not necessary for flow control. With TAQOZ in P2 ROM this should be possible since I have FAT32 already resident, all it needs is an SD card. One advantage of downloading to a named file is that it is also an easy way to transfer source code onto the card. Maybe some of the newer USB serial chips have proper flow control built into them because as we know you can't rely upon the O/S to do it.
    @Peter,
    is this FL something like redirecting serial in into a temporary file on sdcard and then loading from that file so that compilarion/execution is delayed but save?

    Maybe you can answer in the tachyon thread to keep others informed about this. Thanks!

    that is what Peter is saying above in other words.
  • TonyB_TonyB_ Posts: 293
    edited January 4 Vote Up0Vote Down
    Re new MODC/MODZ aliases, shouldn't flag writing be shown in the spreadsheet as compulsory, as with GETRND without D?
    	GETRND            WC/WZ/WCZ
    	MODC    c                WC
    	MODZ    z                WZ
    

    Also, how does the assembler know which of the two instructions called CALLD to assemble?
    Formerly known as TonyB
  • cgraceycgracey Posts: 8,538
    edited January 4 Vote Up0Vote Down
    TonyB_ wrote: »
    Re new MODC/MODZ aliases, shouldn't flag writing be shown in the spreadsheet as compulsory, as with GETRND without D?
    	GETRND            WC/WZ/WCZ
    	MODC    c                WC
    	MODZ    z                WZ
    

    Also, how does the assembler know which of the two instructions called CALLD to assemble?

    Flag writing is not compulsory, though one wouldn't use the instruction without WC/WZ. For self-modifying code, though, we should not make flag writing compulsory.

    The assembler does some sleuthing to know which CALLD to use.
  • Hi guys - long time forum lurker here. Very excited about this finalized image! Looking forward to some P2 hardware!
  • cgraceycgracey Posts: 8,538
    edited January 4 Vote Up0Vote Down
    fixmax wrote: »
    Hi guys - long time forum lurker here. Very excited about this finalized image! Looking forward to some P2 hardware!

    Super! Glad you're on board.
  • I haven't heard much since I put up v31. Is anyone using it?
  • Definitely, I wish I had more to say but everything is going swimmingly although I do need to check out some of the newer changes.
    Tachyon Forth - compact, fast, forthwright and interactive
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  • cgracey wrote: »
    I haven't heard much since I put up v31. Is anyone using it?
    I loaded it onto my Prop123a9 board and ran the blink demo. I also started reading the documentation for LLVM. It looks to be quite a steep learning curve.

  • Seems working. VGA Demos are running well on Prop123-A9.
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