UPDATED 1 February 2017 - Version 15
Single-stepping/interrupts around REP blocks made consistent between cog and hub execution modes
'FLTxx D/#' instructions clear DIR bit and affect OUT bit, read IN bit into C
'DRVxx D/#' instructions set DIR bit and affect OUT bit, read IN bit into C
Note: TESTNIN and TESTIN encodings have switched places
cogs pins RAM Freq CORDIC
Prop123-A9 | 16 18 1024k 80MHz Yes
BeMicro-A9 | 16 18 1024k 80MHz Yes
Prop123-A7 | 8 10 512k 80MHz Yes
DE2-115 | 8 7 256k 80MHz Yes
BeMicro-A2 | 1 10 128k 80MHz No
DE2-Nano | 1 10 32k 80MHz No
NEWEST ZIP FILE:
* 2-clock RDPIN/WRPIN/WXPIN/WYPIN with automatic acknowledge
* 2-clock RQPIN ('read quiet') like RDPIN without acknowledge, allows concurrent reading
* Improved booter ROM now runs at 2M baud, thanks to Jmg's ongoing efforts
* ALTB added to facilitate accessing multi-register bit fields (SETBYTS removed)
* Event jumps added: JINT/JNINT/JCT1/JNCT1...
* SETPEQ/SETPNE replaced with SETPAT, C flag picks INA/INB, Z flags picks equal/not-equal
* Improved booter ROM, now supports 3-pin SPI and half-duplex serial
* ADRA/ADRB renamed to PA/PB
* New 'CALLPA/CALLPB D/#,S/#' instructions write D/# to PA/PB and call S/#
* 4 selectable events for pins, locks, and LUT r/w's
* Direct pin DIR instructions: DIRL/DIRH/DIRC/DIRNC/DIRZ/DIRNZ/DIRN D/#
* Direct pin OUT instructions: OUTL/OUTH/OUTC/OUTNC/OUTZ/OUTNZ/OUTN D/#
* Direct pin IN instructions: TESTIN/TESTNIN D/#
* Increment-test jumps: IJZ/IJNZ/IJS/IJNS D,S/#rel9
* Interrupt-triggering instructions: TRGINT1/TRGINT2/TRGINT3
* Support for Prop123-A7 boards added after Tubular fixed PLL problem
* Support for the BeMicro CV A9 board was added
* Hub/eggbeater can now be 16, 8, 4, 2, or 1 slice of cog and hub RAM
* Fewer slices means lower latency
* Cogs' FIFO's are reduced to match slices now, saving logic
* FPGA images are optimized for their number of slices (not all 16, anymore)
* The Verilog source code is now capable of making any sub-version of Prop2
Improved smart pins:
* Fast 2-clock reads and writes with automatic AKPIN
* Special flag output can go into C on reads
* Pulse mode can now output cycles with custom high and low times
* New reciprocal counter/timer modes for accurate freq/duty measurements
* USB mode now cancels SOP/EOP report on 7+ bit clocks of J or K
* Can now output 1/2/4 bits via RDBYTE sub modes
* Can now input 1/2/4 pins via WFBYTE sub modes
* D/# operand is simplified, S/# used often now for XINIT/XZERO/XCONT
Inter-cog attention mechanism:
* Any cog can request the attention of any/all cogs
* Attention-request event added
* Old write-sensitive hub longs at $FFF80..$FFFBF are gone now
* Even-odd cog pairs can write each other's LUTs now
* New special mode of COGINIT launches even-odd pairs of cogs simultaneously
* Address-selectable read and write events
PINSETM renamed back to WRPIN
PINSETX renamed back to WXPIN
PINSETY renamed back to WYPIN
GETPINZ renamed back to RDPIN
BeMicro CV (A2) support. Two cogs, 128KB hub RAM, and two smart pins.
Prop123-A9 support. All 16 cogs and 1MB of hub RAM.
Transfer input is now double-buffered via XINIT/XZERO/XCONT. You can now stuff two commands before it'll make you wait. There are two new events/interrupts to do with this. One lets you know when you can give it another command without waiting and the other lets you know when it ran completely dry. By using the first-mentioned event as an interrupt, you can do video in the background, while your mainline code executes ~99% of the time. There is an NTSC-by-interrupt example program.
A pixel mixer was added which operates on all 4 bytes between two longs. It can add bytes in-situ, multiply them, alpha blend them, and a bunch of other possibilities via the SETPIX command. 'ADDPIX/MULPIX/BLNPIX/MIXPIX D,S/#' are the commands that do the four-byte operations. 'SETPIV D/#' sets up the alpha-blend factor (8 bits).
Two new commands were added to translate between 8:8:8:0 RGB and 5:6:5 RGB. They are RGBSQZ (squeeze) and RGBEXP (expand). The six instructions below SEUSSR were rearranged to accommodate these new instructions and GETS/GETD were removed.
* improved serial modes
* PINSETM/PINSETX/PINSETY are now 4, 6, or 10 clocks, based on byte, word, or long D/# data.
* PINGETZ is now 4..6, 6..10, or 10..18 clocks, based on byte, word, or long data, according to mode.
* Optional bitfield reordering within bytes for 1/2/4-bpp-LUT streamer modes
* SETQ can now be used before XINIT/XZERO/ZCONT to synchronously adjust streamer frequency at command boundary (see sin_cos_dacs.spin)
* DDS/Goertzel streamer mode can now use limited lookup areas within LUT RAM
* 'REP @label
,##bignumber' bug fixed in PNut.exe
* New VGA 16bpp 5:6:5 RGB demo, thanks to Rayman
* WFBYTE and WFWORD write hub at first opportunity, bypassing the FIFO, meaning data no longer lingers until whole longs are formed
* Color space converter added after Transfer to do RGB->YIQ/YPbPr/YUV/etc conversions
* ALTR/ALTD/ALTS instructions added for doing indirect or base+offset accesses in next instruction
* ALTDS renamed to ALTI
* SETXDAC renamed to SETDACS
* GETPTR instruction added to read back WFxxxx/RFxxxx address - doesn't wrap, though
* GETINT instruction added to read INT1/INT2/INT3 states and event flags (non-destructive)
* SETBRK modified to read back STALLI status and INT1/INT2/INT3 selector settings
* SETCY/SETCI/SETCQ/SETCFRQ/SETCMOD instructions added to support colorspace converter
* Hub exec FIFO-level bug fixed
* GETCNT renamed to GETCT
* The Prop123-A7 board now has 10 cogs, not 11.
* ADDCNT expanded to ADDCT1/ADDCT2/ADDCT3 - three timer events usable as interrupts
* WMLONG added - like WRLONG, but doesn't write $FF bytes, works with SETQ/SETQ2
* 'JMP D' added - CALLD still required for interrupt returns
* SETRDL/SETWRL - related bugs fixed
* C/Z properly restored on RETurns now
* New SETHLK used to set hub LOCK bit event
* GETQX/GETQY waiting improved to allow overlapped CORDIC operations without WAITX
* PNut SUBX bug fixed
* PNut now allows unary NOT/ABS/NEG... instructions (if D-only, D gets used for S)
* PNut fixed for properly-oriented if_00/if_01/if_x0...
Initial debug ISR's have been moved up to $FFFC0..$FFFFF.
Event-triggering LONGs have been moved up to $FFF80..$FFFBF.
(No more complications at the bottom of hub RAM - everything starts at $00000)
PNut doesn't download to the last 16 longs in hub RAM, anymore, so that you don't have to worry about putting those initial debug ISR's in your code.
PNut and the FPGA files are now versioned, with this being v1.
Older zip files: