SOLVED: Creating .rbf files for 1-2-3 FPGA board - any luck??
mindrobots
Posts: 6,506
I'm attempting to create a P1V image from Jac's github repository for the 1-2-3 FPGA board. I've modified the .v file he created for the A9 and Chip's .qsf file for the 1-2-3 FPGA board and gotten what appears to be a good compile.
I use Quartus Files|Convert Programming Files to create a .rbf file based on my .sof file. When I use px.exe to load this to the 1-2-3 FPGA board, it pumps the file down to the board and all looks normal.
On reset of the board (or power on/off), the Conf Status light comes on for a while (expected) and RED0-7 are dimly lit (as normal) but when Conf Status goes out, RED0-7 stay dimly lit - and my image appears to do nothing. (Could be me, could be bad image, could be bad verilog, could be bad .rbf at this point)
If I load the top.rbf from the zip file, it goes through the same reset process but when the COnf Status goes out, RED0-7 are brightly lit and the FPGA image runs.
I built Chip's top example and created a new .rbf from that and it behaves the same as mine.
Has anyone (the other 4 or 5 of us) had any luck building a .rbf file and downloaded their image to the 1-2-3 FPGA board?
I'm wondering if there are some non-default settings for the .rbf file that I am missing from Convert Program Files?
Anybody else trying to play with their 1-2-3 FPGA yet?
I use Quartus Files|Convert Programming Files to create a .rbf file based on my .sof file. When I use px.exe to load this to the 1-2-3 FPGA board, it pumps the file down to the board and all looks normal.
On reset of the board (or power on/off), the Conf Status light comes on for a while (expected) and RED0-7 are dimly lit (as normal) but when Conf Status goes out, RED0-7 stay dimly lit - and my image appears to do nothing. (Could be me, could be bad image, could be bad verilog, could be bad .rbf at this point)
If I load the top.rbf from the zip file, it goes through the same reset process but when the COnf Status goes out, RED0-7 are brightly lit and the FPGA image runs.
I built Chip's top example and created a new .rbf from that and it behaves the same as mine.
Has anyone (the other 4 or 5 of us) had any luck building a .rbf file and downloaded their image to the 1-2-3 FPGA board?
I'm wondering if there are some non-default settings for the .rbf file that I am missing from Convert Program Files?
Anybody else trying to play with their 1-2-3 FPGA yet?
Comments
OK, DON'T USE the Convert Program Files tool - it takes your .sof files and creates binary garbage with the default settings.
DO set up your project to create .rbf files -> Assignments|Device, then click on "Device and Pin Options" then click on "Programming Files" and make sure "Raw Binary File (.rbf)" is checked.
I just loaded the .rbf created directly by the compile (synthesis?) with px.exe and that loaded and ran with the expected results - 8 stopped cogs with COG0 running for a bit when the reset button is pressed.
If someone hadn't left their Prop Plug "elsewhere", they could try some Spin code!
Ok, guys, go create some verilog to run on your 1-2-3 FPGA boards!!!!!