Propeller 1-2-3 FPGA Board (#60054) available to Forum Members $375

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  • jmgjmg Posts: 12,616
    edited June 2016 Vote Up0Vote Down
    Rayman wrote: »
    Can p2 boot from eeprom yet?
    Do you mean i2c EEPROM, or SPI Serial FLASH ?
    With Serial Flash parts down to just over 11c/1k, I'm not sure there are any plans for i2c EEPROMs in the boot sequence ?

  • Yeah SPI serial flash. I don't think Chip has revised the booter for the new instruction set, yet.
  • jmg wrote: »
    Rayman wrote: »
    Can p2 boot from eeprom yet?
    Do you mean i2c EEPROM, or SPI Serial FLASH ?
    With Serial Flash parts down to just over 11c/1k, I'm not sure there are any plans for i2c EEPROMs in the boot sequence ?
    Just out of curiosity, why is EEPROM so much more expensive than SPI serial flash? Are there any advantages of EEPROM over flash?

  • Ok, seems I've forgotten some things... Is there a way to install an SPI flash chip and have P2V boot from it at power up?
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 12,616
    edited June 2016 Vote Up0Vote Down
    David Betz wrote: »
    Just out of curiosity, why is EEPROM so much more expensive than SPI serial flash? Are there any advantages of EEPROM over flash?
    EEPROM usually has higher Cycles (sometimes achieved by adding ECC and extra bits) and EEPROM has more granular writes.

    Serial FLASH usually requires a minimum size erase block, as they erase a whole strip of cells at one time.

    eg looking at Serial Flash 2M Bytes FT25H16, Endurance is >100k cycles and these Erase specs (typs)

    Page pgm ~ 0.4ms (256 Bytes/page)
    Sector Erase ~120ms (4k Byte Sectors)
    32k erase ~200ms
    64k erase ~400ms
    Chip erase ~10s

    I think partial page programs are allowed, but not with any pgm time gains.

    Note those erase times, mean you should round-up to the next largest erase area, when downloading code if you want best speed.
    Because that will vary with vendor, I believe the ROM should not try to be too clever, and instead give the PC side better control access.
  • Rayman wrote: »
    I think I need a new A9 board now, so I can leave this one in P1 mode...

    BTW: How difficult would it be to access the DAC, ADC and colored LEDs?
    I'm doing some P1V/Quartus stuf at the moment.
    Let me know what IO arrangement you want and I can do a build for you.
    i.e.
    PA0..PA15 Green leds
    PA16 RGB leds
    PA17..PA20 Buttons
    PB0..PB31 Header0
    PC0..PC31 DACs and dac clocks



    Melbourne, Australia
  • David Betz wrote: »
    Rayman wrote: »
    Can p2 boot from eeprom yet?
    I thought P2 was going to boot from SPI flash? Has that been changed?

    It will use SPI flash, and I need to port all that software, still, from P2-Hot.
  • jmgjmg Posts: 12,616
    Rayman wrote: »
    Ok, seems I've forgotten some things... Is there a way to install an SPI flash chip and have P2V boot from it at power up?

    If you are doing a PCB, then adding a Boot SPI would be a good idea.
    I think the default stage-1 boot (ROM) is 1 bit SPI only, but wiring a chip as QuadSPI would allow confirm (using streamer?) that Quad/Streamer all works too...

    I think the pins are allocated, but the code is in transit...
  • ozpropdev, I don't really know what I want yet.
    But, if you did that, maybe I could figure out how to change it myself later...
    Thanks.

    This seems like an easy way to get into this P1V stuff.
    Prop Info and Apps: http://www.rayslogic.com/
  • RaymanRayman Posts: 8,882
    edited June 2016 Vote Up0Vote Down
    Anybody know what pins to use for (the coming soon) Boot SPI flash chip?
    Prop Info and Apps: http://www.rayslogic.com/
  • TubularTubular Posts: 3,290
    edited June 2016 Vote Up0Vote Down
    This was my guess based on P2-Hot. Plugs in to top 10 pins of the right-most header.

    However I can see merit in having the CS as the lowest of the 4, that way you could keep drawing downwards for additional chip selects, while keeping the SPI bus on the higher 3

    384 x 429 - 8K
  • jmgjmg Posts: 12,616
    edited June 2016 Vote Up0Vote Down
    Tubular wrote: »
    However I can see merit in having the CS as the lowest of the 4, that way you could keep drawing downwards for additional chip selects, while keeping the SPI bus on the higher 3

    Also keep in mind this needs to support connect to QuadSPI parts too, so that neater CS is unlikely to apply to a quad SPI.
    cgracey wrote: »
    It will use SPI flash, and I need to port all that software, still, from P2-Hot.

    This also raises the point, that even if boot is not going to use Quad itself, it does need to be Quad-safe.
    ie the Quad pins that are connected will need to be allocated and defined during SPI boot.

    ie these pins have dual-modes, and you do not want them floating during boot.

    WP# (IO2)
    HOLD# (IO3) or RESET# (IO3)


    It looks like HOLD# must be high, and it is safe to also have WP# high. Once flipped to Quad MODE, then they become IO2,IO3.

    Addit:
    Just doing a 2016 price refresh, we find 3k+

    Cheapest i2c : $0.07603 SOT23-5 S-24C02DI-M5T1U5 256 x 8 ( 14c for 512 x 8, SOT23)

    Cheapest SPI : $0.12705 TSSOP8 FT25H16T-RB 2M x 8 - can do QuadSPI
    128M SPI : $1.18800 8VDFPN M25P128-VME6TGB

    HyperFLASH : $3.96269 @ 338 BGA24 16M x 8
    HyperRAM: $2.87100/5k BGA24

    SPI flash is certainly now low cost, and will likely be less than the regulator !
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