Running P2 tools on the P2 - Project Oberon ?
jmg
Posts: 15,145
A recent link at arch.fpga led me to this
http://projectoberon.com/
http://www.inf.ethz.ch/personal/wirth/ProjectOberon/index.html
["Project Oberon is a design for a complete computer system. Its simplicity and clarity enables a single person to know and implement the entire system, while still providing enough power to make it useful and usable in a production environment. "]
[" Mostly thanks to the regularity of the RISC instruction set, the size of the compiler could be reduced
significantly. It now measures less than 2900 lines of program and compiles itself in about 3
seconds, which is proof of its efficiency. The entire system compiles itself in less than 10 seconds."]
The whole project fits into a modest sized Spartan 3, with SRAM, and includes all source and verilog.
["This board, Xilinx Spartan-3 by Digilent, features a 1-MByte static memory, which easily accommodates the entire Oberon System, including its compiler."]
The RISC they chose is at the simple end of things ( but it does have floating point op's )
http://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Computer.pdf
but the compiler and code generator are included, so that opens porting the design to a P2, and to benchmarking between original FPGA core, and a P2 variant.
Given the P2 uses a lot more silicon, it should come out ahead, at least on native COG operation
This could be suited to a FPGA board with SRAM, as well as SDRAM, and QuadSPI Flash, or possibly SDRAM and XIP done on the QuadSPI (or a pair/)
http://projectoberon.com/
http://www.inf.ethz.ch/personal/wirth/ProjectOberon/index.html
["Project Oberon is a design for a complete computer system. Its simplicity and clarity enables a single person to know and implement the entire system, while still providing enough power to make it useful and usable in a production environment. "]
[" Mostly thanks to the regularity of the RISC instruction set, the size of the compiler could be reduced
significantly. It now measures less than 2900 lines of program and compiles itself in about 3
seconds, which is proof of its efficiency. The entire system compiles itself in less than 10 seconds."]
The whole project fits into a modest sized Spartan 3, with SRAM, and includes all source and verilog.
["This board, Xilinx Spartan-3 by Digilent, features a 1-MByte static memory, which easily accommodates the entire Oberon System, including its compiler."]
The RISC they chose is at the simple end of things ( but it does have floating point op's )
http://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Computer.pdf
but the compiler and code generator are included, so that opens porting the design to a P2, and to benchmarking between original FPGA core, and a P2 variant.
Given the P2 uses a lot more silicon, it should come out ahead, at least on native COG operation
This could be suited to a FPGA board with SRAM, as well as SDRAM, and QuadSPI Flash, or possibly SDRAM and XIP done on the QuadSPI (or a pair/)
Comments
I'll take a peak, but last time I looked (about 20-30 years ago?) it was a descendant of Pascal - strongly typed, no variable number of arguments to procedures and functions.
I do not think such a port of Wirth's project is useful for the P2 for a multitude of reasons.