Propeller II Counters
jmg
Posts: 15,145
As the design gets near to wrapped up, I'll start a thread for clarifying/expanding docs on Counter operations.
This from the latest Docs, extracting CTR references.
Quadrature counting has some hints of cascade ? - can all counter modes cascade ?
It also mentions half-step, which seems unusual, as most Quadrature devices have 4 steps, one per edge ?
PWM modes - I guess with 1 register for Period, and one for Duty cycle ?
Dual ? modes eg (%010_01001 = dual NCO outputs + dual COUNT_NEGATIVE_EDGES inputs)
Is that Dual CTRA and Dual CTRB (for 4 counting registers ?) or Dual as in CTRA+CTRB ?
How does dual COUNT_NEGATIVE_EDGES inputs select the pins to use for edges ?
Interactions are unclear, where
%111_01011 = dual PWM outputs + dual COUNT_POSITIVE_EDGES inputs
can that give 2 True PWM outputs, (same periods, separate Duty values ? ), and also total edges on 2 pins ? per Counter ?
That would infer 5 registers : WrDualPeriod,WrDutyX,WrDutyY, RdEdgesM,RdEdgesN ? (repeat for CTRA, CTRB ?)
CAPCTRS ? ( & SETCTRS) - Is that S plural, so gives atomic software capture (write?) of both CTRA and CTRB on the same CLK edge ?
Is there any hardware edge -> capture, or only software ?
Are ctr pins always SysClk sampled, or is there an external prescaler possible, before the Pin-sync ?
(that allows higher MHz inputs, without needing high SysCLK settings, saving power )
This from the latest Docs, extracting CTR references.
CTRA SETCTRA/SETWAVA/SETPHSA/ADDPHSA/SUBPHSA/GETPHZA/POLCTRA/CAPCTRA/SYNCTRA CTRB SETCTRB/SETWAVB/SETPHSB/ADDPHSB/SUBPHSB/GETPHZB/POLCTRB/CAPCTRB/SYNCTRB SYNCTRA wait for PHSA to roll over SYNCTRB wait for PHSB to roll over COUNTERS - this section is not done yet!!! Each cog has two configurable counters. They are named CTRA and CTRB and are accessed by thirteen instructions each. The instructions which end in "A" are for CTRA and those that end in "B" are for CTRB. For brevity, only CTRA instructions are used in the definitions and examples that follow. GETPHSA D - Get PHSA into D GETPHZA D - Get PHSA into D, simultaneously clear PHSA to 0 GETCOSA D - Get COSA into D GETSINA D - Get SINA into D SETCTRA D/# - Set CTRA configuration SETWAVA D/# - Set WAVA SETFRQA D/# - Set FRQA SETPHSA D/# - Set PHSA ADDPHSA D/# - Add to PHSA SUBPHSA D/# - Subtract from PHSA SYNCTRA - Wait for PHSA to roll over POLCTRA WC - Check if PHSA has rolled over (C=1 if rolled over) CAPCTRA - Capture CTRA accumulators into COSA and SINA Modes: (QDR = PHS[31] XNOR PHS[30], or PHS[31] delayed by 90 degrees) Off Mode ------------------------------------------------------------------------------- %00000 = Counter off (initial state after cog start) NCO Modes ------------------------------------------------------------------------------- %00001 = NCO output + video PLL mode, PLL output = PHS[31] (reference signal) %00010 = NCO output + video PLL mode, PLL output = PHS[31] times 8 divide by 32 %00011 = NCO output + video PLL mode, PLL output = PHS[31] times 8 divide by 16 %00100 = NCO output + video PLL mode, PLL output = PHS[31] times 8 divide by 8 %00101 = NCO output + video PLL mode, PLL output = PHS[31] times 8 divide by 4 %00110 = NCO output + video PLL mode, PLL output = PHS[31] times 8 divide by 2 %00111 = NCO output + video PLL mode, PLL output = PHS[31] times 8 divide by 1 %01000 = NCO output DUAL Modes ------------------------------------------------------------------------------- %000_01001 = dual NCO outputs + dual COUNT_LOWS inputs %001_01001 = dual NCO outputs + dual COUNT_HIGHS inputs %010_01001 = dual NCO outputs + dual COUNT_NEGATIVE_EDGES inputs %011_01001 = dual NCO outputs + dual COUNT_POSITIVE_EDGES inputs %100_01001 = dual NCO outputs + dual TIME_LOWS inputs %101_01001 = dual NCO outputs + dual TIME_HIGHS inputs %110_01001 = dual NCO outputs + dual TIME_NEGATIVE_EDGES inputs %111_01001 = dual NCO outputs + dual TIME_POSITIVE_EDGES inputs %000_01010 = dual DUTY outputs + dual COUNT_LOWS inputs %001_01010 = dual DUTY outputs + dual COUNT_HIGHS inputs %010_01010 = dual DUTY outputs + dual COUNT_NEGATIVE_EDGES inputs %011_01010 = dual DUTY outputs + dual COUNT_POSITIVE_EDGES inputs %100_01010 = dual DUTY outputs + dual TIME_LOWS inputs %101_01010 = dual DUTY outputs + dual TIME_HIGHS inputs %110_01010 = dual DUTY outputs + dual TIME_NEGATIVE_EDGES inputs %111_01010 = dual DUTY outputs + dual TIME_POSITIVE_EDGES inputs %000_01011 = dual PWM outputs + dual COUNT_LOWS inputs %001_01011 = dual PWM outputs + dual COUNT_HIGHS inputs %010_01011 = dual PWM outputs + dual COUNT_NEGATIVE_EDGES inputs %011_01011 = dual PWM outputs + dual COUNT_POSITIVE_EDGES inputs %100_01011 = dual PWM outputs + dual TIME_LOWS inputs %101_01011 = dual PWM outputs + dual TIME_HIGHS inputs %110_01011 = dual PWM outputs + dual TIME_NEGATIVE_EDGES inputs %111_01011 = dual PWM outputs + dual TIME_POSITIVE_EDGES inputs WAVE modes ------------------------------------------------------------------------------- %01100 = dual SQR_WAVE output + GOERTZEL input %01101 = dual SAW_WAVE output + GOERTZEL input %01110 = dual TRI_WAVE output + GOERTZEL input %01111 = dual SIN_WAVE output + GOERTZEL input In the WAVE modes, <snipped> LOGIC Modes ------------------------------------------------------------------------------- %10000 = LOGIC_A_POSEDGE input INA & !INA previous %10001 = LOGIC_NA_AND_NB input !INA & !INB %10010 = LOGIC_A_AND_NB input INA & !INB %10011 = LOGIC_NB input !INB %10100 = LOGIC_NA_AND_B input !INA & INB %10101 = LOGIC_NA input !INA %10110 = LOGIC_A_NE_B input INA <> INB %10111 = LOGIC_NA_OR_NB input !INA | !INB %11000 = LOGIC_A_AND_B input INA & INB %11001 = LOGIC_A_EQ_B input INA == INB %11010 = LOGIC_A input INA %11011 = LOGIC_A_OR_NB input INA | !INB %11100 = LOGIC_B input INB %11101 = LOGIC_NA_OR_B input !INA | INB %11110 = LOGIC_A_OR_B input INA | INB %11111 = LOGIC_ENCODER input INA, INB encoder OUTA = ADD signal (condition met or LOGIC_ENCODER forward step) OUTB = SUB signal (LOGIC_ENCODER reverse step) In the LOGIC modes, FRQ is conditionally added to PHS on each clock cycle that meets that mode's requirement. In the case of the LOGIC_ENCODER mode, FRQ may be added or subtracted to/from PHS when a half-step is registered. OUTA and OUTB reflect the ADD and SUB states for each cycle, and are more likely to be useful by other CTR's, rather than being sent to output pins. --LS 1110011 0L I CCCC DDDDDDDDD SSSSSSSSS SETCTRS D/#,S/# (ctrb,ctra) --L- 1111111 xx L CCCC DDDDDDDDD x10110000 SETCTRA D/# --L- 1111111 xx L CCCC DDDDDDDDD x10111000 SETCTRB D/# ---- 1111111 xx x CCCC xxxxxxxxx x11011101 CAPCTRA ---- 1111111 xx x CCCC xxxxxxxxx x11011110 CAPCTRB ---- 1111111 xx x CCCC xxxxxxxxx x11011111 CAPCTRS ---- 1111111 xx x CCCC xxxxxxxxx x11100000 SYNCTRA (waits for ctra if single-task, loops if multi-task)) ---- 1111111 xx x CCCC xxxxxxxxx x11100001 SYNCTRB (waits for ctrb if single-task, loops if multi-task))
Quadrature counting has some hints of cascade ? - can all counter modes cascade ?
It also mentions half-step, which seems unusual, as most Quadrature devices have 4 steps, one per edge ?
PWM modes - I guess with 1 register for Period, and one for Duty cycle ?
Dual ? modes eg (%010_01001 = dual NCO outputs + dual COUNT_NEGATIVE_EDGES inputs)
Is that Dual CTRA and Dual CTRB (for 4 counting registers ?) or Dual as in CTRA+CTRB ?
How does dual COUNT_NEGATIVE_EDGES inputs select the pins to use for edges ?
Interactions are unclear, where
%111_01011 = dual PWM outputs + dual COUNT_POSITIVE_EDGES inputs
can that give 2 True PWM outputs, (same periods, separate Duty values ? ), and also total edges on 2 pins ? per Counter ?
That would infer 5 registers : WrDualPeriod,WrDutyX,WrDutyY, RdEdgesM,RdEdgesN ? (repeat for CTRA, CTRB ?)
CAPCTRS ? ( & SETCTRS) - Is that S plural, so gives atomic software capture (write?) of both CTRA and CTRB on the same CLK edge ?
Is there any hardware edge -> capture, or only software ?
Are ctr pins always SysClk sampled, or is there an external prescaler possible, before the Pin-sync ?
(that allows higher MHz inputs, without needing high SysCLK settings, saving power )