Prop2 arrives today - but it won't work
cgracey
Posts: 14,133
When doing our presentation on the Prop2 on Saturday afternoon, Beau noticed something that wasn't right as he zoomed into the synthesized logic layout. It turns out that some poly density fill we added to the blank standard cells was conflicting with actual circuitry. We didn't realize that the 'fill' cells were sometimes placed in non-integral positions, overlapping onto adjacent circuitry. So, these chip's coming in today are not going to work. We will only be able to do a power-up test on the I/O ports, which doesn't tell us much. We must resubmit the design database without the fill patterns and get this fabricated again on the next shuttle run. So, it will be another 8 weeks, or so, before we might have functional Prop2 chips.
Beau said when he saw that poly conflict, he got a really sick feeling, hoping it was maybe just a mistake in the database he was displaying. I remember his mood changing during the presentation, but didn't know what to make of it. He verified afterwards that it was, indeed, a problem. It didn't occur to either of us that there would have been anything to see there, as that block was delivered to us already checked. Our attempt to meet minimum poly density requirements backfired, unfortunately.
Beau said when he saw that poly conflict, he got a really sick feeling, hoping it was maybe just a mistake in the database he was displaying. I remember his mood changing during the presentation, but didn't know what to make of it. He verified afterwards that it was, indeed, a problem. It didn't occur to either of us that there would have been anything to see there, as that block was delivered to us already checked. Our attempt to meet minimum poly density requirements backfired, unfortunately.
Comments
Sorry to hear that - but like David says, we have the FPGA versions to work with meanwhile :-)
I know how I feel when I order a bunch of circuit boards and find something wrong. This is about 100X costlier...
Well, we have the FPGA and lots of work to do. Docs, libraries, examples, learning, etc...
Thanks for telling us the current state of things. It is really appreciated.
Plus like David says, we'll have a little more time to get our software ready for the big day!
But a request for all of our customers. Let's not use this as an opportunity to encourage additional design improvements to Fozzy Bear. These changes could open up more synthesis, I/O frame changes and lots of expense. The cost of design changes and running chips is so much more than the $60,000 shuttle runs mentioned on Saturday - it includes synthesis consultants, salaries, administrative costs, quick-turn packaging, mask sets, etc. Even small changes could take six months or a year and have mounting costs quickly heading to a half-million USD. For this reason many chip companies favor small iterations and improvements to their design. Each one provides a new product and an opportunity to sell all over again to the same customers.
USB support, Ethernet, really advanced graphics controls are examples of things I hope not to see encouraged at this time. All we want to do is get these metal layers straight and go back to the foundry.
*I* for one do not intend to ask for any hardware features (ie changes to P2)
I am pushing for software-only USB & Ethernet that does not require any changes to the P2 - and I only push for that so that P2 will have a better chance for success
Then we could certainly use this time to make software drivers.
I've been reading your other messages and would be happy to support some work in this area, but must keep a close watch on financials due to the additional expenses we're about to face. Whatever volunteer efforts could be accomplished will quickly bring your mug shot to the Parallax Hall of Fame.
That's unfortunate but part of life I suppose.
As Baggers said we should look on this as an opportunity to get the software ready for the release, there is a lot to do!
And Ken, you are right we should actively discourage any changes, it will only add to delays and increase costs.
Onwards and upwards!
We don't need a moving target at this point. We just need to get working what we've already started.
Thanks, I'll talk with wifey... however starting Wednesday, I am going to be tied up for the next 2-3 weeks with something urgent (non-prop).
Preliminary calculations show that we may need to wait for P2 before 10Mbps Ethernet can fit into a cog. It may be barely possible in two cogs on a DE2-115, but it would be very tricky.
A 160Mhz P2 will have 16 clock cycles to handle each bit, which should be more than sufficient.
Low speed USB (1.5mbps) should not be a problem even on the 60Mhz fpga's; 12mbps may need to wait for real silicon as only 5 clocks would be available per bit on the fpga.
The low hanging fruit to tackle is low speed, maybe with HID (for keyboard and mouse support) and serial drivers (even though low speed serial is against spec, it seems to work for the AVR guys)
Hmm... but this is the wrong thread to discuss this.
Also, just curious, what's the cost of the design change just to fix this poly problem?
Hang in there, guys! This, too, shall pass.
-Phil
My heart goes out to you. I know that horrible sinking feeling. But hey, we have a two month delay, after all this time it's not such a big deal. (yeah I know it's expensive, but a delay at the end is much the same as a delay at the start and such things happen.).
Anyone following your developments would know that now is not a good time to be suggesting any changes and enhancements.
It's like zooming into a city on Google maps and checking out the houses.
I'm totally amazed he could see the problem from those images.
I'm puzzled how this actually happens ? - My PCB software has a DRC for such clearance errors, and surely poly density fills are only allowed into 'space left over' ? Does this mean someone else pays for the layers that need fixing ?
Even worse, if there is no (reliable) DRC, what else maybe lurking as a failure ?
Chip or Beau will have to answer this, but I'll give you the layman interpretation. The P2 was designed in two different software environments. Beau designed the outter frame, I/Os, A/D in his tool and the internal guts of the processor were synthesized in another tool. Both tools are very expensive and they don't play too well together. There are export/import formats that can get our design into their synthesis tool but with limited overall system checks. For me, I take comfort seeing what's being done by our developers in the DE2-115 FPGAs and knowing that the entire P1 was designed manually, like the P2 I/Os.
We pay for the layers that need fixing. When you submit a design to a foundry, the customer takes all responsibility for failed process checks. It's like they're just making a cake with ingredients you specify, or printing a PDF from your artwork.
I have checked with my experts and it appears that the female socket for the Prop2 board is not available on EBay.
They are available elsewhere... for free:) But I hate to ask for samples because I'm not an engineer and I really have no plans
to buy hundreds of parts.
Any chance I can pay you guys to put a few in a bag? Or better yet... let's have Jeff(oldbit) do it:)
Rich
That's a scary sounding blind spot, that really needs a firm fix.
If you can export the poly-fill as a separate layer, then some of the better Gerber tools can do layer-layer clearance checks, purely on geometry (ie they do not expect any data-intelligence)
Another approach is to force the poly-fill to lowest-priority, but that is more complex and involves multi-photo imaging.
Oh man!! Here I was ready with only 40-50 needed changes I was going to be demanding!!! :-)
Now you'll become part of the Muppet Show! Better change your avatar to Kermit the Frog.
I'm having so much fun with the new Project Board that is has taken my mind off the P2, (Except for all the excitement on hearing Chip talk about it this weekend.)
Carry one Gracys. Your doin' good.
Jeff
Which one would you like, DE0-Nano or DE2-115?
Just for that I won't tell you what any of my great ideas are!!!
I doubt I could convince Altera to give Propellerpowered academic prices, so I'd better order I just ordered the DE0-Nano.
Thanks Chip
Jeff