Shuttle today?

David BetzDavid Betz Posts: 14,192
edited 2013-01-08 - 10:47:52 in Propeller 2
Isn't this the day that Ken said that P2 would be submitted to the January shuttle run? If so, how soon can Parallax expect test chips?

Comments

  • Ken GraceyKen Gracey Posts: 6,919
    edited 2013-01-07 - 09:48:44
    We'll let you know when it's submitted, for certain.

    Today is the most recent deadline provided to us by the synthesis/shuttle company. There may be more flexibility in the deadline but I'm not certain until we connect this morning. This morning Beau is hunting an electrical rule check short from a layout vs. schematic failure. There's a short or open. A failed LVS requires another six hours of processing time, and we're currently waiting for a prior check to finish.

    We shall let you know how it works out.
  • David BetzDavid Betz Posts: 14,192
    edited 2013-01-07 - 09:52:12
    Ken Gracey wrote: »
    We'll let you know when it's submitted, for certain.

    Today is the most recent deadline provided to us by the synthesis/shuttle company. There may be more flexibility in the deadline but I'm not certain until we connect this morning. This morning Beau is hunting an electrical rule check short from a layout vs. schematic failure. There's a short or open. A failed LVS requires another six hours of processing time, and we're currently waiting for a prior check to finish.

    We shall let you know how it works out.
    Good luck! In the meantime, some of us will continue to have fun with the FPGA emulations! :-)
  • Beau SchwabeBeau Schwabe Posts: 6,432
    edited 2013-01-07 - 12:41:03
    The LVS errors Ken mentioned have been found and corrected. They were human errors caused in the process of adding density metal... I'm running right now what should be a final LVS. Started at 2pm (CDT) ... the LVS run takes about 6 hours to complete over the complete Propeller II chip.

    Once complete there is a slight amount of cleanup before streaming out the database. ... I'll be checking back at about 8pm (CDT) to see what the results are.
  • David BetzDavid Betz Posts: 14,192
    edited 2013-01-07 - 12:54:34
    The LVS errors Ken mentioned have been found and corrected. They were human errors caused in the process of adding density metal... I'm running right now what should be a final LVS. Started at 2pm (CDT) ... the LVS run takes about 6 hours to complete over the complete Propeller II chip.

    Once complete there is a slight amount of cleanup before streaming out the database. ... I'll be checking back at about 8pm (CDT) to see what the results are.
    Thanks for the update! It's amazing how much interesting status information we get from you guys!
  • potatoheadpotatohead Posts: 10,121
    edited 2013-01-07 - 14:21:50
    Seconded! I find learning about the process very interesting and enlightening. Really appreciated and fingers crossed the check doesn't uncover something else.

    Amazing really. The sheer number of potential things that could botch an effort defies ordinary imagination. Not sure how you do it guys.
  • Ken GraceyKen Gracey Posts: 6,919
    edited 2013-01-07 - 14:44:02
    Since everybody can handle real engineering details, we're not making the submittal today. At this point we have a new approach to take prior to the February 20th deadline - submit it as soon as possible, before February 20th! Taiwan celebrates Chinese New Year and will take time off, which is why the next deadline is 40 days beyond today. That means shuttle run chips back by the Expo in May.

    Do I think we'll make it? YES, of course! But not until Chip finally tires, putting the final brush strokes on the ROM, and until Beau says it all checked out okay are we ready. Caught an e-mail today where Chip slipped in a minor ROM change and Beau said "no big deal" and then Beau said he's going to bed (this afternoon!) while an LVS runs in the background. This kind of activity happens near the end [or the beginning!].

    They're close, really close, but I can't promise anything because it's research and development.
  • mindrobotsmindrobots Posts: 6,506
    edited 2013-01-07 - 15:11:30
    Thanks for being up front and honest as usual. We appreciate the truth more than what we WANT to hear!
  • David BetzDavid Betz Posts: 14,192
    edited 2013-01-07 - 15:13:27
    Ken Gracey wrote: »
    Since everybody can handle real engineering details, we're not making the submittal today. At this point we have a new approach to take prior to the February 20th deadline - submit it as soon as possible, before February 20th! Taiwan celebrates Chinese New Year and will take time off, which is why the next deadline is 40 days beyond today. That means shuttle run chips back by the Expo in May.

    Do I think we'll make it? YES, of course! But not until Chip finally tires, putting the final brush strokes on the ROM, and until Beau says it all checked out okay are we ready. Caught an e-mail today where Chip slipped in a minor ROM change and Beau said "no big deal" and then Beau said he's going to bed (this afternoon!) while an LVS runs in the background. This kind of activity happens near the end [or the beginning!].

    They're close, really close, but I can't promise anything because it's research and development.
    Thanks for the update! Maybe I should start making plans to attend UPEW this year! :-)
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-01-07 - 15:35:22
    Thanks for the update - no use making a shuttle run until P2 is READY!
    Ken Gracey wrote: »
    Since everybody can handle real engineering details, we're not making the submittal today. At this point we have a new approach to take prior to the February 20th deadline - submit it as soon as possible, before February 20th! Taiwan celebrates Chinese New Year and will take time off, which is why the next deadline is 40 days beyond today. That means shuttle run chips back by the Expo in May.

    Do I think we'll make it? YES, of course! But not until Chip finally tires, putting the final brush strokes on the ROM, and until Beau says it all checked out okay are we ready. Caught an e-mail today where Chip slipped in a minor ROM change and Beau said "no big deal" and then Beau said he's going to bed (this afternoon!) while an LVS runs in the background. This kind of activity happens near the end [or the beginning!].

    They're close, really close, but I can't promise anything because it's research and development.
  • Cluso99Cluso99 Posts: 16,935
    edited 2013-01-07 - 15:43:20
    Thanks for the info/update. We all appreciate the openness and honesty of Parallax.
  • Roy ElthamRoy Eltham Posts: 2,933
    edited 2013-01-07 - 16:17:39
    Ken,
    For what it's worth, I think you guys made the right choice. :) Sure, it means more delay before we get chips, but it's better to be more certain about what you submit.

    David Betz, you should definitely come to the Expo!
  • potatoheadpotatohead Posts: 10,121
    edited 2013-01-07 - 16:31:57
    I totally agree on that being the right choice. Love the plan Ken!
  • cgraceycgracey Posts: 13,125
    edited 2013-01-07 - 20:08:34
    This will give us opportunity to fix any bugs we discover in the next few weeks. There is one problem that I'm aware of: When you do a JMPTASK, the REPS/REPD mechanism is not cancelled for any affected task that is using it. This takes some extra instructions to account for now. A small Verilog change would take care of this. It may not be worth doing, though, if we don't find some other problem or significant improvement to make.
  • Beau SchwabeBeau Schwabe Posts: 6,432
    edited 2013-01-07 - 20:15:28
    Just a heads up... the 8pm LVS was clean.

    I'm waiting for a last minute revision on the ROM code that Chip wants to address.
    In the mean time I'm making a backup of the database, and will go one more time around the perimeter where Parallax's IP meets the synthesized logic core to double check power and ground connections to make sure as many are in there as possible. (Perhaps a brief video of what the so called 'perimeter' looks like from my perspective.)

    The hard part I feel is over, and it's too bad that we just barely missed the deadline today ... after LVS runs to make sure that everything is intact and doesn't break along the way, there just aren't enough hours in the day to get very many iterations.
  • Ym2413aYm2413a Posts: 630
    edited 2013-01-07 - 22:02:47
    I don't mind the small delay. I'm just glad that progress is being made!
    Super excited for the new chip. So its well worth the wait.
  • Cluso99Cluso99 Posts: 16,935
    edited 2013-01-07 - 22:40:06
    Great news Beau. It's is a shame to miss the shuttle by such a small margin. However, I see Chip has found a problem with the tasking that he would like to solve. We have another couple of weeks to keep trying the emulation anyway so this is keeping some of us occupied (and very grateful to Parallax for releasing the emulation).
  • SapiehaSapieha Posts: 2,964
    edited 2013-01-07 - 22:55:45
    Hi All.

    As I understand need to made Propeller II as fast as possible --- I don't understand why some of people will hurt to made IC (even if it still have some bug's)

    In my opinion --- We have now FPGA emulation
    > Lets us test it extensively to find that bug's before IC will be made.
    That save Parallax money and us many frustration on end IC product


    Ps. All that have 6 COG's version can help more that we that have NANO on some tests --- As COG to COG comunication and like ---> so start work instead of ask every time on SHUTTLE DAY!
  • User NameUser Name Posts: 1,451
    edited 2013-01-08 - 10:47:52
    Ken Gracey wrote: »
    Since everybody can handle real engineering details, we're not making the submittal today.

    I think Terasic just sold a few more FPGA boards. :)
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