Cluso's Propeller OS V1.14 - now with SPIN/PASM Compiler, EEPROM Read/Write :)



  • Of course it's slower than parallel SRAM, but fetching the bytes as required from SPI or whatever is even slower (~0.4 MT/s = 0.8 MHz Z80 (?) (altough I think the Z80 doesn't use (almost) every memory cycle like the 6502)). OTOH this amount of code
    mov t1,address
    shr t1,shift
    and t1,mask1
    mov t2,t1
    add t1,cachetags_ptr
    rdlong t1,t1
    and t1,mask2
    cmp t1,t2 wz
    if_nz jmp #fetchline
    and address,mask3
    add address,cachedata_ptr
    rdbyte data,address
    to read a single byte is quite a ton. (even more when writing,due to having to tag the line as dirty)
  • Cluso99Cluso99 Posts: 15,219
    edited 2019-05-04 - 21:29:13
    Not sure who you arguing with/against?

    I use parallel SRAM with unbuffered and seperate address and data lines directly from the propeller. Cannot get any faster than this. Just copy the address to the pins and read/write the data to another set of 8 pins, together with /CS, /WE and /OE pins.
    FWIW my RamBlade uses 8 data, 19 address, plus 3 control lines (30 pins) to the SRAM.

    SPI has to have the command, address and data sent (clocked) out serially. Much slower, even if quad or 2xquad is used.

    Caching adds comparisons to check if the data is in cache or not, and if not then the command and address has to be sent out and then data read/written in a block.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Not arguing with anyone. Just random thoughts on what could be done with what I already have here (which is serial RAM).
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