Lowest Power Consumption

wass

I've been looking around, but can't find this spec anywhere. What's the lowest power consumption of an SX28 (or SX18) at a given voltage? At 3V, I've measured this to be about 110uA using an external clock essentially at DC. Power consumption seems to be about flat until the clock rate gets above 30KHz, so I'm guessing that this (110uA) is the quiescent power consumption with the watchdog timer disabled, the comparator disabled, no brown-out detection and no feedback resistor, all i/o pins set to output with no load and no pull-ups enabled. Has anyone measured or read about a lower power level?

Of course dropping the voltage to 2.5 Volts cuts down the power consumption a bit, but I'm wondering if the SX can get down into the few uA range without going to SLEEP. I'm also wondering why the power consumption is relatively high when there's apparently nothing clocking in the chip.

Thanks,
-Katie

David B

Have you seen the data sheet SX20AC-SX28AC-Data-v1.6.pdf from the Parallax SX Software and Documentation web page?

It has a lot of current draw information; maybe not exactly what your're asking, but very close. For one thing, it specifies a 9 uA draw under some conditions.

wass

Thanks, I do have that spec shhet and have stdied it throughly.

I find that under "power down" it's 1uA typically, 9uA max. Power down is SLEEP mode and the current consumption is so low I can't even measure it accurately, in practice. I'm looking to find the minimum active supply current, with an arbitrarily low clock speed at a given voltage.

If you look at the current vs clock frequency graphs they are close to linear with frequency, this should be the case with CMOS logic. But from my measurements this doesn't hold true when frequencies are very low. There seems to be a floor to the current consumption line (not shown in the graphs) of around 100ua at 3V. The "active supply current vs Vdd" graph hints at this floor, but I'm looking for an actual spec.

-Katie