PDA

View Full Version : Troubles with Sigma-Delta ADC



slosjo
09-21-2007, 11:10 PM
Hello all-

I am trying to implement a Sigma-Delta ADC object into my code.· After I call the ADC object, I am using PropTerminal to monitor·a variable being set by the ADC.· The results are not what they should be and·I'm not sure what I am doing wrong or weather it is a software or hardware issue.· If anyone is interested in offering up some advice, let me know and I will send you my code and/or elaborate more on my problem.·

Thanks



·

Mike Green
09-21-2007, 11:20 PM
Please post your code and your schematic as well as a description of what problem you're seeing. The Sigma-Delta ADC is sensitive to switching noise and the components need to be mounted close to the Propeller if you're going to run it at high speed (as the ADC object does).

Rayman
09-22-2007, 12:05 AM
I was just thinking that the electret microphone circuit on the propeller demo board is something of a sigma-delta ADC... It uses P8 as a 1-bit quantizer, P9 and the 100k resistor as the 1-bit DAC and the 1-nF caps as the integrator/summer. Is this what you are doing? Or, do you have an external IC for it?

slosjo
09-22-2007, 01:38 AM
That is basically what I am doing. The analog input is the voltage across a potentiometer which ranges from about 0.4VDC to about 3VDC. This goes through a 150K resistor and then to an input pin. Connected to the input pin are also 2 - 1nF ceramic caps, one going to VSS and the other to VDD. There is a 100k resistor going from the input pin to a feedback pin. I connected everything on the prototype board to the pin access holes around the outside of the prop.

Rayman
09-22-2007, 01:43 AM
Then, it sounds like you could just borrow code from the "Microphone2VGA" example that digitizes the microphone. Parallax has made good use of counter module to do the digitization.

slosjo
09-22-2007, 01:55 AM
I looked at that code, and I think that I have it working now, at least sort of. I may have more questions shortly.

Thanks

slosjo
09-22-2007, 02:27 AM
Well it looks as though my ADC is not working as well as I thought.· The value is supposed to be between 0 and 255, and I am getting some change in the value as I change the pot, but it's not very stable, and not·even close to 255.· I have attached the ADC code and hardware specifics·that i'm using if anyone would like to have a look.

Thanks



Post Edited (slosjo) : 9/21/2007 6:36:38 PM GMT

Mike Green
09-22-2007, 02:50 AM
The ADC code is pretty straightforward and looks fine.

Try slowing everything down. Instead of using an 80MHz clock, try a 40MHz clock, then a 20MHz clock, etc. by changing _clkmode to pll8 or pll4, etc. If the problem is noise or reflections, etc., slowing down the clock should help. The serial debug routines should adjust their timing since the clkfreq function is normally used to calculate timing for drivers that are speed dependent.

slosjo
09-22-2007, 03:05 AM
Ahhh good call Mike.· That helped a lot with the stability issue, but I'm still not getting the range that I should.· I changed my sample bits to 8, so I should be getting a range from just over 0 to just under 255.· I'm getting something like 20 or so to about 70.· My voltages on the analog input pins are about 0.4 - 2.8.· Also, should I be doing x := getvalues.read1 >>2· ?

Rayman
09-22-2007, 03:06 AM
Isn't that 150k resistor way too big?·

What is the resistance of your pot?· It need to be much smaller that 150k...

Post Edited (Rayman) : 9/21/2007 7:27:15 PM GMT

slosjo
09-22-2007, 03:35 AM
The pot is a max of about 5.5k

Rayman
09-22-2007, 03:59 AM
Maybe replace the 150k with 100k. I think then that when Vin is VCC, the ADC input pin will be at Vcc/2. Right now, if the ADC input were all 1s then the feedback would be a constant 0 and the ADC input voltage would be Vcc/2.5, below the trigger threshold of Vcc/2.

slosjo
09-22-2007, 04:08 AM
That makes sense. I will give it a try, thank you very much.

Mike Green
09-22-2007, 04:45 AM
slosjo,
You're not going to get a range from 0 to 3.3V. Actually, 0.4 to 2.9 sounds pretty good. Don't forget that the output (feedback) pin doesn't really switch from 0 to 3.3V. There are some voltage drops in the output switching transistors. If it's important to get a wider range, you could use an op-amp on the input to the ADC with an offset of about 0.4V and less than unity gain. That would transform a range of 0-3.3V to something more like the 0.4-2.9V that the ADC can handle.

The ">> 8" I suggested before was based on your using 14 bit resolution and was just a way to focus on the significant bits (given the noise involved). You could leave out the shift entirely if you think the numbers you're seeing are valid.

Tracy Allen
09-22-2007, 05:26 AM
Hi slosjo,

I'd posted a circuit analysis for Prop Sigma-Delta at
this link. (http://forums.parallax.com/showthread.php?p=633577)
It might help with the choice of resistors for the range.
With 100k for feedback and 150k for input, and a prop threshold of 1.65 volts nominal, the range calculated range should be a count of 68 at 2.8 volts input up to a count of 191 at 0.4 volts input.

count = (2^bits) * (1.65*(R1+R2) - (R2 * Vin)) / (3.3 * R1)
R1=input ohms
Vin=input voltage
1.65=threshold voltage
3.3=Vdd-Vss
bits=bits in result, eg WAITCNT N=256 cycles for 8 bit result
count= change in phsx register in N cycles, result.

I don't know why you're only seeing 20 to 70. You asked if you should be "doing x := getvalues.read1 >>2 ?". I don't think so. Why?

P.S. Edited it to use the names stated. I had first posted it with cell references from an Excel spreadsheet. As Mike points out, the result depends too on the drive capabilities of the totem pole output transistors and on the exact threshold level of the input transistors.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Post Edited (Tracy Allen) : 9/21/2007 11:50:30 PM GMT

Rayman
09-22-2007, 07:14 AM
Anybody know why we need 1nF caps to both VCC and ground? Wouldn't just one 2nF cap to ground do exactly the same thing? I don't get it...

Phil Pilgrim (PhiPi)
09-22-2007, 07:22 AM
It helps to reduce the effects of noise on Vdd. Since the input threshold is Vdd/2 at any particular instant, a capacitive divider will keep the sampling node at this level in a noisy environment better than just a capacitor to ground would.

-Phil

Tracy Allen
09-23-2007, 01:54 AM
As Phil pointed out, the Prop has a CMOS threshold of Vdd/2. It is not a TTL type threshold referenced to ground. The double capacitor technique is predicated on having equal levels of noise on both Vdd and Vss, so both squeeze in or stretch out at the same time. That is what you might expect from pulses of current that pass through equal wiring resistances on their way into the Vdd and out of the Vss pins. But it won't do so much good if the wiring is haphazard, or if there is high current sourcing and sinking happening at other Prop I/O pins, being reflected unequally on the two supplies at the points where they feed the two ADC capacitors. The idea is to keep the wiring short and to consider what would generate noise across those capacitors or the signal source. Here are two threads that are informative about these issues:
Initial efforts, bad results halfway down the thread, Chip is puzzled too. (http://forums.parallax.com/showthread.php?p=576072)
Chip got it working! (http://forums.parallax.com/showthread.php?p=576575)
The ADC circuit on the new demo board reflect those insights.

Remember too that the sigma-delta technique causes the input pin to hover exactly at its input threshold. Both input transistors are partly turned on. According to Chip, the input transistors have a relatively small geometry, and by my measurement the totem pole current due to them hovering at threshold is around 1 or 1.5 milliamps. That fluctuates wildly as the sigma-delta action is taking place, alternately driving the pin just below and just above threshold. That is another reason to to pay close attention to the layout, and that is especially true when the clock frequency is high.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

slosjo
09-24-2007, 09:23 PM
Hello all-

I just read Chip Gracey's example about Sigma Delta ADC conversion and he said that he used surface mount components extremely close to the pins. Has anyone done a successful sigma delta using the holes surrounding the·propeller·on the prototype board to connect their inputs and capacitors? If so, please elaborate on the specifics of your connections because I am having troubles with mine and still getting very unstable results.

Thanks

Post Edited (slosjo) : 9/24/2007 1:32:40 PM GMT

deSilva
09-25-2007, 01:00 AM
Some aspects of ADC are still a "black art". I know this remark is not particularly helpful, but should be taken as a warning to expect too much of a "low cost solution" when going > 10 kHz.

Maybe using a "real" comparator rather than a Prop pin will improve things much (reasons for this given by Tracy)
Absolutely stable power supply is a "must": Do you have at least 200nF close at the Prop power pins?

slosjo
09-25-2007, 01:44 AM
I have a 1nF cap going to VDD and a 1 nF cap going to VSS(through hole ceramic caps). I connected them to the analog input pins' access hole on the prototype board and cut the leads as short as physically possible. I used these values because they were suggested by the author of the ADC code that I posted above.

deSilva => "Absolutely stable power supply is a "must": Do you have at least 200nF close at the Prop power pins?"

Are you referring to the caps I described above, connected to the analog input pin?

cgracey
09-25-2007, 01:28 PM
Here are some other things to consider...

Output/direction signals for pins 0-15 run right-to-left on the die, going through OR gates beginning with Cog7 and ending at Cog0. So Cog0 has the shortest drive path to pins 0-15. Furthermore, the last series OR coming from Cog0 has very short wires to pins·7 and 8. So, having a low-numbered cog drive pins physically close to Cog0 is very low-latency, which matters greatly at 80MHz, but not at 40MHz.

Conversely, output/direction signals·for·pins 16-31 run left-to-right on the die, going through OR gates beginning with Cog0 and ending with Cog7. So, Cog7 has the shortest drive path to pins 16-31. And from Cog7, the wires connecting to pins 23 and 24 are quite short, keeping latency minimal.

This right-to-left·and left-to-right arrangement was to keep worst-case wiring lengths at half of what they would have been, had all pin-control signals·begun at Cog0 and ended at Cog7, or vice-versa. even so, the worst-case output/direction signal delay through 7 cogs is only about 1.5ns.

For inputs, all cogs see the same signals at the nearly the same time, as there are no series-gate delays. There is a slightly increasing wire delay from pin 7 down to 0, pin 8 up to 15, pin 23 down to 16, and pin 24 up to 31. The·worst-case input signal wiring delay·is about 500ps. These wiring delays affect both inputs and output signals.

So, the best sigma-delta cog/pin combinations would be Cog0 using pins 7 and 8, and Cog7 using pins 23 and 24.

There is one more source of delay, and that is the I/O pad, itself. It takes about 500ps to translate an input to a driven internal signal which goes to all the cogs. It takes about 700ps to translate an output signal to a pad voltage. This means that the best case output-to-input loop delay is ~1.2ns (700ps + 500ps). The worst case is that value plus max wiring delays both directions and 1.5ns for 7 series-ORs. This would sum to 4ns. That's a big chunk of a 12.5ns (80MHz) cycle and it eats greatly·into the feedback time.

What can really mess things up are parasitic capacitances and inductances due to PCB/breadboard wiring. They make the on-chip delays seem like nothing. If you look at the microphone·layout on the Propeller Demo Board, you'll see that wires were kept to just a few millimeters and small SMT parts were used. Also, pins 8 and 9 were chosen to keep on-chip wire delays to a minimum, especially when driven with a low-numbered cog.

And as was said earlier, having identical sigma-delta filter caps to both VSS and VDD keep power supply noise balanced at the input. This makes a big difference·over having·just·one to VSS or one to VDD.


▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔


Chip Gracey
Parallax, Inc.

Post Edited (Chip Gracey (Parallax)) : 9/25/2007 5:36:31 AM GMT

deSilva
09-25-2007, 02:27 PM
slosjo said...
Are you referring to the caps I described above, connected to the analog input pin?

Funny idea - I was referring to a 100 to 200nF cap between the POWER pins, close to the chip! From your words I assume you have none :-(

Rayman
10-17-2007, 03:59 AM
I just went to work on a dual-ADC in single COG object this morning and already have it working :) Started from the Microphone2VGA example. I'm using fairly long leads on the Prop demo board proto area and it seems to be working fine... Now, just need to add a VGA GUI...

Rayman
10-17-2007, 05:37 AM
One thing I'm not clear on is how to select values for the two capacitors of the divider... It seems that Parallax picked values that, with the feedback resistor, give an RC time of 200us, about the same as the sample period at 12-bits, as in the demo. But, I'm not sure if they did this on purpose, or how much it really matters...

Anybody up on Sigma-Delta ADC theory?

deSilva
10-17-2007, 07:10 AM
First order Delta-Sigma modulation is not such a black art. You will find some explanations here in some threads (see Tracy's resistor computations) as well as all over the web...

The basic idea is - looking at the Demo Board circuit - to keep the cap(s) at some voltage level (Vdd/2 to be precise) by feeding it exactly enough current from the Prop (or drawing from it) as is drawn from/fed to the external source. This is accomplished by some sort of PWM (>50%: feeding, <50% drawing). The program logic is another thing but the "electrical" idea is quite simple. So to be able to fast react to a change of voltage the cap must not be too large, as you might not be able to provide the needed charge by your pulses. On the other hand a tiny cap will not allow you to use the full pulse width of your signal, thus reducing the possible dynamic range.

Allowing a full voltage swing each T will require a C around T/2R; a smaller cap will reduce the dynamic, a larger will generate distortion at higher frequencies (low pass characteristic)

The R at the Prop feedback pin depends on the situation at the signal source - you have to adapt to its output impedance.. See Tracy's computations...

Post Edited (deSilva) : 10/16/2007 11:35:02 PM GMT

Rayman
10-17-2007, 07:38 AM
The way I'm looking at it is that the voltage between the capacitors is fixed at Vdd/2. The Prop is then a variable current source that feeds these capacitors to maintain the voltage. The maximum current into the capacitors is Imax=(Vdd-Vdd/2)/R1 and the minimum current is Imin=-(Vdd/2)/R1 (where R1 is the resistor between the Prop output pin and the capacitors). This current is exactly balanced by Iin from the voltage source being measured, limited by the resistor between it and the caps, R2, so Iin=Vin/R2. You can find the upper limit in Vin by equating Iin and Imax and the lower limit in Vin by equating Iin and Imin.

But, what I don't know is how to pick the best value for the capacitors :)

deSilva
10-17-2007, 07:43 AM
Have you read my posting above?

Rayman
10-17-2007, 07:49 AM
Yes, but I'm still not sure what to do for capacitor values... I guess I'll try equating the RC time on the prop side to the sampling period (while making sure the RC time on the input side is fast enough for the input frequency...)

deSilva
10-17-2007, 07:59 AM
Funny man! I told him that his damned cap and the output impedance of his signal source form a low pass, and that the feed back resistor has to be choosen so that the Prop can "equalize" the charge flow.
And he says he is unsure how to chose the capacity. Sigh....

Graham Stabler
10-17-2007, 08:13 AM
deSilva,

You shouldn't get upset when people don't seem to read or understand your posts, it's not always their fault, sometimes your posts are hard to understand for a variety of reasons (readers technical background, English, formatting, "comedy").

Having said that it's important to spend at least as much time reading replies as the person spent typing them.

Graham

Rayman
10-17-2007, 08:31 AM
deSilva: You're speaking in general terms about things I already know... I'm looking for equations for capacitor values based on clock speed, #bits, etc...

deSilva
10-17-2007, 04:07 PM
So you understand all the elements - why do you ask then? Put them all together!
What do you think the clock speed can have to do with it?
Aha, there is another low pass filter at the Prop feed back pin http://forums.parallax.com/images/smilies/smile.gif But do we need to care?

Post Edited (deSilva) : 10/17/2007 9:10:15 AM GMT

deSilva
10-17-2007, 05:27 PM
So let's put is this way:
You need a certain charge to change the voltage at a cap:

Q = C * V

The feedback current just tries to do this. It is of no concern in what way: Charge is charge!

So when you want to compensate for a voltage change per time you must not use a capacity that need more current for it than you can deliver:
dQ/dt >= C * dV/dt
approximately:
C <= I/(V * f)
So if your current is limited by a (feed back) resistor R, this is
C <= 1/( f R)
which should not astonish you http://forums.parallax.com/images/smilies/smile.gif

Values: f = 10 kHz, R = 100k --> C <= 1nF

-----------------------------
On the other hand you have some "latency" or reaction time, before you start your current feed-back business...
This is the "clock". If the source gets a chance to fill up (or empty) the cap before you can intervene, you have lost... However this cannot happen when the clock is much faster than the bandwidth limited signal. Note that the cap C is working as part of this low pass filter, so everything is quite "automatical"

But it is important to adapt the feed back resistor to the input current... When the involved voltages are similar, a current limiting resistor around R will be fine.

-----------------------------
The tricky things are to consider parasitary capacities and inductancies...

Post Edited (deSilva) : 10/17/2007 10:03:20 AM GMT

Rayman
10-17-2007, 07:13 PM
DeSilva: Yes, it's the RC between the prop and the cap that I wondering about...

Let's say R1 is from prop to caps and R2 is from caps to input...

The desired voltage range fixes the ratio of R1 to R2.
The desired frequency response fixes the ratio of R2 to C.

But, what to use for optimal values? R1 is limited on the low end by the rated drive ability of the chip... But, I think there must be a fundamental relationship for optimal R1*C time relative to the Prop sampling rate. It appears that in the Microphone2Vga example and the demo board, they are using an R1*C time equal to the sampling rate.

But, I don't know if this is a good "rule of thumb", or how much it really matters...

deSilva
10-17-2007, 09:38 PM
I think Rayman put the problem to the point: There is still one degre of freedom you can work with. R*C will be fine, but why not use 100 Ohms and 1 uF?

Indeed, why not?

The only reason I can think of is to generally keep any flow of current as low as noise will allow. But is that not just one of the problems: noise? All right, so shun megohms! But higher currents generate magnetic fields, and inductance is something a hobby electronicist shuns even more http://forums.parallax.com/images/smilies/smile.gif

Many considerations go beyond "theory". We need a very "good" cap: Fast switching (80 MHz), little inductance. This costs at higher values...

Parasitic effects are in the order of 10 pF, so we should stay right above 100pF


So I think you could scale C between 10 nF and 100pF, changing the resistors accordingly to 1M or 10k.

Most important is the low pass effect to the signal source!

I am not aware of any impact of the clock. As I said: charge is charge!
So 80MHz worstcase through 100k to 1 nF looks like a NO-OP http://forums.parallax.com/images/smilies/smile.gif But it IS loading the cap! This is whats it's all about with low pass filters...

Post Edited (deSilva) : 10/17/2007 4:30:44 PM GMT

Rayman
10-17-2007, 10:19 PM
deSilva: Exactly.

But, I think maybe this degree of freedom is not so free... I've read a little theory that leads me to believe that the RC time on the Prop side is an additional low pass filter on the response (I guess I'm going to have to test this...).

The clock and bits determine the sampling rate, which is a third low pass filter on the response. Generally, one oversamples and then digitally filters to reduce quantization noise.

Graham Stabler
10-17-2007, 10:27 PM
Sampling rate determines bandwidth because of nyquist (sampling rate must be twice highest frequency component) but for a specific sampling rate I can't see why there would be further low pass filtering effects. Perhaps I'm missing your point.

What is this theory you have read?

Graham

deSilva
10-17-2007, 11:24 PM
I tried to make clear that there is no "analogue" low-pass effect to be considered by the feed-back signal. I don't know how to explain it - I tried it twice and Rayman keeps ignoring this http://forums.parallax.com/images/smilies/smile.gif

I like the following article.. I must confess I didn't understand it at the first reading some months ago, but after some experience with delta-sigma it makes much sense to me...
www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html (http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html)

Post Edited (deSilva) : 10/17/2007 3:33:41 PM GMT

Tracy Allen
10-18-2007, 02:19 AM
I've heard that the choice of RC time constant for the feedback is made so that the voltage at the input will change less than or equal to one bit during one clock period. One bit is equivalent to Vdd/Nbits. E.g., Vdd/4096 for 12 bits. The change during that time is,
(Vdd * clkperiod) / (2 * R * C).
Equating the two makes Vdd drop out and Nbits = 2 * R * C / clkperiod. For example, the demo board uses R=100k and C=1nf, and clkperiod=12.5ns, so Nbits=16000 or about 14 bits. Of course, external noise sources are a separate issue. One could rearrange that formula to calculate the RC required given the number of bits. R is chosen to be large relative to the output resistance of the mosfets.

Now, the thing is, I don't remember where I heard that and I don't see a quick theoretical or rule of thumb explanation for it. In particular, what are the consequences of making it much less or much larger, in terms of speed of transient or frequency response, vs accuracy? I started out on a gedanken experiment, imagining the extremes of zero capacitance and infinite capacitance. In the first case, it turns into a comparator with three possible states (always high, always low, or oscillating at clkfreq), and you have to wait three clock periods (two transitions) to get the first level of confidence in the current state. On the other hand, with infinite capacitance, you have to wait forever to get any information at all. There is a lot of territory between the extremes, and there may be an optimum in there somewhere. Maybe a pretty wide optimum.

One sort of counterintuitive notion is that the step response of the sigma-delta is instantaneous, in the sense that if the input current takes a sudden step, the modulator pattern immediately alters to the new one appropriate to the new current, however, it takes time for the observer of the bit stream to realize that the pattern has changed. For example, if the input step is from Vdd/2 to 2*Vdd/3, then the modulator immediately shifts from the 1:1 pattern to the 2:3 pattern and the observer can realize part of that change in only a few cycles, but it will take many more cycles for the observer to obtain enough information to determine if the input is really something not exactly 2:3 but say more like 200:303.


@deSilva, that is a very nice reference in Elektronik, thanks. It is true as the author says that a lot of the material written is opaque, and alternative glib explanations can miss a lot of the counterintuitive nature of delta-sigma (or sigma-delta if you prefer). The article however gives little insight about the pending question of how to choose the capacitors for the Prop. Opaque too in that respect.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Rayman
10-18-2007, 02:32 AM
Thanks Tracy. I think this is close to saying that the RC time on the Prop side is equal to (some factor times) the sample period, where the sample period is clock period*2^SampleBits, right?

Rayman
10-18-2007, 02:51 AM
slosjo,

If you're still out there, I've just posted my own dual-adc object code. Might help you with yours...

Ray

Peter Verkaik
10-18-2007, 03:14 AM
Tracy, you may well have read it in the SX forum.
I posted some ADC calculations there once.
Attached is a reworked text that has the outcome you mentioned.

Edit: I forgot to edit the line below the diagram.
New file attached.

regards peter
·

Post Edited (Peter Verkaik) : 10/17/2007 7:42:51 PM GMT

Rayman
10-18-2007, 03:51 AM
Well, I've experimentally found that very large capacitor values still work when you average a large number of samples together to get the result, but individual samples are all either 0, 50, or 100% ...


Just tried it with no capacitors at all:· Still works!· Maybe even less noisy than with the 1nF caps!

deSilva
10-18-2007, 04:38 AM
@Rayman, @Tracy: I am happy to hear that you are slowly converging to the opinion I try to express for nearly a day now. I know those situation. Someone explains something that is not quite obvious to you, you say "No, that cannot be the case, look this is why..." then your own awareness process starts, and after some rearrangements of your own notions you sometimes find the same words as the person who - seemingly in vain - tried to explain it to you.

This is sometimes the situation I find myself here in this a forum. I read a posting, and I think: "But these are my words from two postings above", "But I explained this to him in the beginning, didn't I?"

So to summarize: Yes this is all so, and there is no "I have heard" and "Why, even without an external cap".

The question of "work" has to include "noise" and "aliasing". This is why I found the referenced article quite instructive.....

All explanations lead to the same conclusions.
(a) Classically considering the input RC combination as a lowpass filter, after which the signal is - logically! - sampled with twice the filter frequenciy
(b) More in the spirit of the delta-sigma theory seeing the cap as an "incremental" integrator, needing just enough capacity to hold the charge swing during one clock cycle.

I said above that - as the clockfrequency even for 2 bit conversion is many times the signal bandwidth, we need not bother with it.

This however was wrong! It refered to the situation that the signal is in fact already bandwidth limited. But this is not necessarily the case. It is it AFTER the RC lowpass, but not IN THE PROCESS of being compensated for by the feed-back clock pulses!

So the "oversampling" is (also) needed to be fast enough to compensate for the higher frequency parts of the signal.

So the reasoning is that:
(1) Tell me the bit resolution you need
(2) I tell you the oversampling needed for it (2^N)
(3) Tell me your clock rate
(4) I tell you the bandwidh you can handle, in terms of f and RC
(5) You tell me your pet values for the Rs (low current at the Prop, other considerations at the signal output)
(6) I tell you the C

Post Edited (deSilva) : 10/17/2007 8:46:16 PM GMT

Ken Peterson
10-18-2007, 07:46 AM
@Rayman:· I already made a dual ADC object for use with my touch screen driver.· Works great, and I used through-hole components as well.·· My effective range on the touch screen is about 20% to 80% of the voltage range, but that does seem to be adequate.· I included a routine in the touch screen object to calebrate it using screen coordinates and corresponding touch readings.

I have included it again here in case anyone's interested.


▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔


The more I know, the more I know I don't know.· Is this what they call Wisdom?

Post Edited (Ken Peterson) : 10/17/2007 11:54:58 PM GMT

Tracy Allen
10-18-2007, 03:29 PM
Peter,
My analysis was very similar to yours, although I cheated. I linearized the charging curve in the limit of a one bit change around Vdd/2. That is easier but not as general as the RC exponential that you solved.


from
I = C dV/dt
rearrange
dV = I dt / C
and substitute I = (Vdd/2)/R for the incremental current around the sig-delta set point in the Prop.
dV = Vdd*dt / (2*R*C)
and then require dV to be a change of one bit, i.e., dV = Vdd/Nbits where Nbits = 2^bits
and dt is the duration of on time slot, e.g. 12.5ns on a Prop at 80 mhz
Vdd/Nbits = Vdd * dt / (2 * R * C)
and then rearrange,
R * C = dt Nbits /2 = dt * 2^(bits-1)


That is the same as your result using the exponentials. I'm not sure where I first became aware of this analysis. Maybe I cooked it up out of thin air, or maybe i saw your earlier post, or maybe I am "slowly converging to the opinion (the estimable deSilva) try to express for nearly a day now" It seems like a reasonable thing to do, but despite the calculation I am not on a solid footing of why it is(?) correct and what metric to use for a further sensitivity analysis.

I find it most productive to have things explained from several different angles, beginner's mind. There is always the possibility that there is a clear explanation for things when stripped down to fundamentals. Also there is the possibilty that fundamental aspects of a tricky problem like this have never been explored.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

deSilva
10-18-2007, 05:12 PM
@Tracy , thank you for your remark(s) http://forums.parallax.com/images/smilies/smile.gif
I can even FEEL your uneasiness in this simple matter.... I think I also looked at the system diagrams with the same uneasiness some months ago.

http://forums.parallax.com/attachment.php?attachmentid=49949

And then it made sense suddenly :

- The "Adder" - oh, yes thats where the both currents (!) from the input and the feedback through these high value resistors meet. And the counter issues an inverted pulse at the feed-back pin in this mode - how clever they thought of that!

- The "Integrator" - oh, yes: a cap of course. But does it really integrate? Just "a little bit", it gives a stabilized point of voltage reference in the first place, around the trigger threshold.... It could be called a "virtual integrator" for this reason. So its value only matters wrt its "swing" around this point of reference, a "swing" due to the high frequency parts of the signal - the parts much above(!) the used bandwidth, that will not be eliminated immediately by the "overclocked" feed-back pulses. Oh, I really "see" the noise here http://forums.parallax.com/images/smilies/smile.gif And how it vanishes by oversampling...

- The "Comparator" - oh, yes: Very good thinking to have inputs switching straight at Vdd/2

- The "Sample and Hold", well thats what a counter is made for http://forums.parallax.com/images/smilies/smile.gif

- The "Feed-back" - oh, yes - an ingenious design of an seemingly "exotic" counter mode!

Post Edited (deSilva) : 10/18/2007 9:30:35 AM GMT

deSilva
10-18-2007, 05:42 PM
Rayman said...
Just tried it with no capacitors at all: Still works!

Maybe my answer to that got lost... You are using the 6 to 10 pF Propeller input pin capacitance. This is fine, as the formula derived above just says
C <= something
When you have no "natural" highter frequency parts (as with your quasi static pot) then the missing low pass will do no harm.

Post Edited (deSilva) : 10/18/2007 11:20:15 AM GMT

deSilva
10-18-2007, 07:13 PM
Rayman said...
Well, I've experimentally found that very large capacitor values still work when you average a large number of samples together to get the result, but individual samples are all either 0, 50, or 100% ...

And I also forgot to answer to this...
This is not so much an effect of the cap, but you have a changed RC now! The formula said:
C < 1 nF for 10kHz
So when using - say: 10uF - you have an immense latency of 1 second! There is no useful information within smaller intervals.
In other words: It takes time to recharge such a large cap through such high resistors.

I am sure you have not changed the resistors; to have the old situatioin again you should change them to 100 Ohms, needing a buffering for the input...

Post Edited (deSilva) : 10/18/2007 11:18:08 AM GMT

Rayman
10-18-2007, 09:23 PM
Thanks everyone.



R * C = dt Nbits /2 = dt * 2^(bits-1)


This seems to make a lot of sense to me now.· The frequency response of this ADC is fundamentally limited by the Nyquist frequency, which is half the sampling rate = 1/(dt*Nbits).· So, in order not to reduce the frequency response, we·want the cutoff frequency, 1/(2PI*RC), to be about the same.

But, why you wouldn't want an even smaller value for RC isn't perfectly clear to me...· I suppose this would have something to do with the effective number of bits of the digitization...

deSilva
10-18-2007, 09:48 PM
No.
A smaller RC will bring you into aliasing trouble...

Post Edited (deSilva) : 10/18/2007 1:53:45 PM GMT

slosjo
10-18-2007, 09:53 PM
Rayman-

I actually have mine working now. It turns out that when you have everything soldered properly and neatly, things work much better.

Peter Verkaik
10-18-2007, 10:50 PM
R*C = Ts*2^(N-1) = (2^(N-1))/Fs where Fs = 1/Ts is the sample frequency
The condition is in fact
R*C >= (2^(N-1))/Fs
and it assures the accuracy is within 1 LSB every DAC pulse.

The second condition for R*C is determined by the input bandwidth
R*C = 1/(2*pi*Fi) where Fi is the highest input frequency.

So if you have a given input bandwidth, calculate R*C and
adjust Fs and/or the resolution N to match the first condition.

If you have a given Fs, you can calculate what input bandwidth
you can use at specific resolutions.

regards peter

Rayman
10-18-2007, 11:18 PM
Peter, I tried using a really big C, and it didn't work very well... Individual samples all had values of 0, 50, or 100%. (This is with DC input)
So, I think there must be some upper limit on RC as well, regardless of the input frequency.

Peter Verkaik
10-18-2007, 11:46 PM
I used >= in the first condition to make clear
it is the lowest possible value to use.
It does not mean you can increase the C
value to any extent, as deSilva explained a few
posts earlier, without decreasing the resistors.

So the RC value to use is the nearest value above
the calculated value, that you can easily create
from standard resistor and capacitor values.

regards peter

Rayman
10-19-2007, 01:58 AM
I made a little Web Applet here:

http://www.pulsedpower.net/Applets/Electronics/SigmaDeltaADC/SigmaDelta.html

to help look at things...

Peter Verkaik
10-19-2007, 02:49 AM
Nice.
Just a few remarks.
You mention Ts = (2^N - 1)/Fs (3rd equation)
I assume you mean to calculate C*R there
which is (2^(N-1))/Fs
Also, that formula is only valid when R1=R2 (R = R1/2) and C1=C2 (C = 2*C1)
then C*R = (2^(N-1))/Fs
I have not checked it but with different R1 and R2, I guess R equals (R1*R2)/(R1+R2)·.
Since C1 = C2 all the time, just name both capacitors C.

regards peter

Peter Verkaik
10-19-2007, 03:00 AM
You may want to incorporate level shift (1 extra resistor, R3 in schematic on following pages)
Original german page:
http://www.sprut.de/electronic/pic/programm/compadc/compadc.html
Translated to english by google page:
http://www.google.com/translate?u=http%3A%2F%2Fwww.sprut.de%2Felectronic %2Fpic%2Fprogramm%2Fcompadc%2Fcompadc.html&langpair=de%7Cen&hl=en&ie=UTF8

The above pages are based upon the Microchip appnote AN700:
http://www.e-sonic.com/whatsnew/Microchip/signal/AN700.pdf


regards peter

Post Edited (Peter Verkaik) : 10/18/2007 7:13:05 PM GMT

Rayman
10-19-2007, 03:08 AM
Peter,

Ts there is just that given by the #bits and the clock frequency. And, Fs is just the inverse of this.

I want to add something about this (2^(N-1))/Fs, but I still coming to grips with it... Instead, I just put in the frequencies corresponding to R1*2*C and R2*2*C. If I figure this stuff out, I'll put in what you and Tracy are saying...

Rayman
10-19-2007, 03:13 AM
Peter,

I did actually come up with this level shifter idea myself yesterday! Actually, since the voltage between the caps is kept fixed at Vdd/2, things are a lot like the situation with opamps... So, you can form an analog summer by just bringing in any number of voltages through resistors.

That level shifter is a 3-way summer, summing the input/R2, Vdd/R3, and Vss/R4...

Ray

Peter Verkaik
10-19-2007, 03:15 AM
My point was that Ts = ((2^N)-1)/Fclk (as displayed on your page) should be (2^(N-1))/Fclk
as given by the C*R equation.

regards peter

Rayman
10-19-2007, 03:18 AM
Peter,

The Ts there (maybe I should rename it) is just the time it takes the Prop to take a sample....

Peter Verkaik
10-19-2007, 03:31 AM
I see. So your Ts is the total time to convert a new value of N bits
and the Fclk is the rate at which the output pin is pulsed (oversample frequency).

regards peter

Peter Verkaik
10-19-2007, 05:34 PM
Rayman,
I made a document with 5 steps to calculate the component values.
If you find any errors in these calculations, let me know.
The calculations include shift levels.

regards peter

Rayman
10-19-2007, 08:12 PM
Peter,

Thanks. Looks good. I still have to think some more about "Step 5"!

Tracy Allen
10-20-2007, 02:02 AM
I'm skeptical about the calculation of input bandwidth, F2 in Raymond's, which uses the input resistor R2 only, and step 4 in Peter's, which uses the Rp combination of all three resistors. The problem is similar to the summing node of an op amp, in the sense that due to feedback, the voltage on the capacitor does not have to change (or the change is the output change divided by the open loop gain). The same thing may be true here in the limit of high oversampling. That is to say, to first order, choosing 200k resistors instead of 100k resistors does not imply 1/2 the bandwidth per the formulas. Or, the choice of capacitor does not have as strong effect on bandwidth as implied by the formulas. The references cited do not address this issue. One thing that is quite different for an op amp is that hanging a capacitor from the summing node to ground raises the gain at high frequencies and leads to instability, depending on phase delays in the op amp itself. In the Prop, the sampling phase delay is always precisely one cycle, far higher in frequency than an input one would expect to appy.

I also have problems with the formulas relating RC to the bit rate (F1 or step 5). I understand the mechanics of the math. There is more to it though, as the actual feedback frequency (the details of the bit pattern) is strongly dependent on the instantaneous signal magnitude. I'm not saying my skepticism is justified, I'm just saying I'm not convinced and haven't had time or insight to think it through to prove something one way or another. It's the justification for the math that eludes me.

The one thing that is certain is that it takes Ts = 2^N clock cycles to acquire an N bit sample, and traditional oversampling starts from there. 2 / (2pi*Ts) to reach Nyquist, and much more to really connect the dots at the chosen resolution. There is no problem with the analysis at DC, for choosing the resistor values based on range. Everyone agrees with that, and the addition of the two extra resistors to set the range is very useful too.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Rayman
10-20-2007, 02:14 AM
I'm skeptical of my F1&F2 calculations also! I'm starting to think it is very much like an opamp in a feedback circuit though. In this case, maybe there's a Gain-Bandwidth product that matters. I'll have to check if this is what Peter is calculating...

Peter Verkaik
10-20-2007, 04:54 AM
Here are my latest calculations.
The outcome is indeed different for Fs.

Charge: voltage at outpin = Vdd

Uin·· Vdd·· Vdd·· Ut·· Ut·· Ut·· Ut····· dUt
--- + --- + --- - -- - -- - -- - -- - 2C*--- = 0
R1··· R2··· R3··· R1·· R2·· R3·· R4····· dt

Let Rp = R1//R2//R3//R4 and Cp = 2C then

Uin··· Vdd···· Ut····· dUt
--- + ------ - -- - Cp*--- = 0
R1··· R2//R3·· Rp····· dt

Let Ut = Umin*e^(-kt) + A - A*e^(-kt)

dUt
--- = -k*Umin*e^(-kt) + k*A*e^(-kt)
dt

Substituting Ut and dUt/dt

Uin··· Vdd···· Umin·········· A··· A
--- + ------ - ----*e^(-kt) - -- + --*e^(-kt) + Cp*k*Umin*e^(-kt) - Cp*k*A*e^(-kt) = 0
R1··· R2//R3··· Rp··········· Rp·· Rp

Substituting t=infinity

Uin··· Vdd···· A······························ Uin··· Vdd
--- + ------ - -- = 0····· ----->····· A = Rp*(--- + ------)
R1··· R2//R3·· Rp····························· R1··· R2//R3

Substituting t=0

Uin··· Vdd···· Umin
--- + ------ - ---- + Cp*k*Umin - Cp*k*A = 0
R1··· R2//R3··· Rp

··· Uin··· Vdd···· Umin
··· --- + ------ - ----
··· R1··· R2//R3··· Rp································ 1
k = -------------------··· Substituting A yields k = -----
······ Cp*(A - Umin)································ Cp*Rp

Discharge: voltage at outpin = 0

Uin·· Vdd·· Ut·· Ut·· Ut·· Ut····· dUt
--- + --- - -- - -- - -- - -- - 2C*--- = 0
R1··· R3··· R1·· R2·· R3·· R4····· dt

Let Rp = R1//R2//R3//R4 and Cp = 2C then

Uin·· Vdd·· Ut····· dUt
--- + --- - -- - Cp*--- = 0
R1··· R3··· Rp····· dt

Let Ut = Umax*e^(-kt) + B - B*e^(-kt)

dUt
--- = -k*Umax*e^(-kt) + k*B*e^(-kt)
dt

Substituting Ut and dUt/dt

Uin·· Vdd·· Umax·········· B··· B
--- + --- - ----*e^(-kt) - -- + --*e^(-kt) + Cp*k*Umax*e^(-kt) - Cp*k*B*e^(-kt) = 0
R1··· R3···· Rp··········· Rp·· Rp

Substituting t=infinity

Uin·· Vdd·· B······························ Uin·· Vdd
--- + --- - -- = 0····· ----->····· B = Rp*(--- + ---)
R1··· R3··· Rp····························· R1··· R3

Substituting t=0

Uin·· Vdd·· Umax
--- + --- - ---- + Cp*k*Umax - Cp*k*B = 0
R1··· R3···· Rp

··· Uin·· Vdd·· Umax
··· --- + --- - ----
··· R1··· R3···· Rp································ 1
k = ----------------··· Substituting B yields k = -----
···· Cp*(B - Umax)······························· Cp*Rp

Charge: at t=Ts
Ut(Ts) = Umin*e^(-kTs) + A - A*e^(-kTs) = Umax

Discharge: at t=Ts
Ut(Ts) = Umax*e^(-kTs) + B - B*e^(-kTs) = Umin

Subtracting:
-(Umax-Umin)*e^(-kTs) + (A-B) - (A-B)*e^(-kTs) = Umax-Umin
·················································· ·····················Vdd
(A-B)*(1-e^(-kTs)) = (Umax-Umin)*(1+e^(-kTs)) = Uripple*(1+e^(-kTs)) = ---*(1+e^(-kTs))
·················································· ·····················2^N
·········· Vdd···· Vdd···· ······· 1··· 1··· 1··· Rp
A-B = Rp*(------ - ---) = Rp*Vdd*(-- + -- - --) = --*Vdd
··········R2//R3·· R3··· ········ R2·· R3·· R3··· R2

Rp····················· Vdd
--*Vdd*(1 - e^(-kTs)) = ---*(1 + e^(-kTs))
R2····················· 2^N

Removing Vdd and writing out:

Rp·· Rp············ 1···· 1
-- - --*e^(-kTs) - --- - ---*e^(-kTs) = 0
R2·· R2··········· 2^N·· 2^N
·········· Rp··· 1···························· Rp··· 1··· (2^N)*Rp
·········· -- - ---··························· -- + ---·· -------- + 1
·········· R2·· 2^N··························· R2·· 2^N····· R2
e^(-kTs) = --------····· ----->····· e^(kTs) = -------- = ------------
·········· Rp··· 1···························· Rp··· 1··· (2^N)*Rp
·········· -- + ---··························· -- - ---·· -------- - 1
·········· R2·· 2^N··························· R2·· 2^N····· R2

······· Ts······· (2^N)*Rp·········· (2^N)*Rp
k*Ts = ----- = ln(-------- + 1) - ln(-------- - 1)
······ Cp*Rp········ R2················ R2

Using approximations ln(x+1) = ln(x) + (1/x) and ln(x-1) = ln(x) - (1/x)

·Ts······ 2*R2············································ 2^(N-1)·· 2^(N-1)·· 2^(N-2)
----- = -------- ·----->· (2^N)*Ts = 2*Cp*R2· ----->· Fs = ------- = ------- = -------
Cp*Rp·· (2^N)*Rp·········································· · Cp*R2···· 2C*R2···· C*R2

Total conversion time Tc = (2^N)*Ts = 2*Cp*R2 = 4*C*R2

I think I got it right now. Comments please.

regards peter

Post Edited (Peter Verkaik) : 10/19/2007 9:30:24 PM GMT

Rayman
10-20-2007, 08:18 AM
If Tc is given, do you want 4*C*R2<=TC ?

I'm surprised it doesn't depend on R1. I would have thought it would go with R2/R1

Peter Verkaik
10-20-2007, 11:51 AM
I am even more surprised that Rp drops out totally.

Summarizing:
Given the design parameters Uinmin and Uinmax, and selecting a value for R1,
we can calculate R2, R3 and R4. This leaves C to be determined.

Fs > 2*Fin· (Nyquist)

Fs*Tc = 2^N

C = Tc/(4*R2)

So there are 3 more design parameters: Fs, Tc and N
two of which you can select, the 3rd is then set.
Often Fs is determined by the program and the used oscillator frequency
so you can either select Tc or N.

Edit:
Since the realtime conversion time is in fact given by the actual used Fs and N,
it may be better to leave Tc out of the calculation until Fs and N are set.

Fs*Tc = 2^N· with Tc = 4*C*R2 becomes

Fs*4*C*R2 = 2^N

C = (2^N)/(4*R2*Fs)
So select N·and Fs and calculate C
Select the larger standard C value that is nearest to the calculated value.
(larger to keep the ripple at the summing node within 1 LSB)

Tc = (2^N)/Fs
If·Tc is too large, either decrease N or increase Fs and recalculate C.

regards peter


Post Edited (Peter Verkaik) : 10/20/2007 5:03:44 AM GMT

Peter Verkaik
10-20-2007, 06:55 PM
I investigated the approximation I used to find C a bit more
and found a new condition!

Note on the approximation:

······· Ts······· (2^N)*Rp·········· (2^N)*Rp
k*Ts = ----- = ln(-------- + 1) - ln(-------- - 1) can be rewritten as
······ Cp*Rp········ R2················ R2

······· Ts·············· R2················ R2
k*Ts = ----- = ln(1 + --------) - ln(1 - --------)
······ Cp*Rp········· (2^N)*Rp·········· (2^N)*Rp

Taylor:
ln(1+x)········ = ln(1+(+x)) =· x - (x^2)/2 + (x^3)/3 - (x^4)/4 + ....
ln(1-x)········ = ln(1+(-x)) = -x - (x^2)/2 - (x^3)/3 - (x^4)/4 - ....
ln(1+x)-ln(1-x) = 2x + 2*(x^3)/3 + 2*(x^5)/5 + ....
··············· = 2x * (1 + (x^2)/3 + (x^4)/5 + ....)· where 0 < x < 1

·································· R2····················R2
This gives a new condition: x = -------- < 1··· ---->··· -- < 2^N
······························· (2^N)*Rp·················Rp

···················· R2
Assuming that x = -------- is much smaller than 1, then ln(1+x)-ln(1-x) = 2x
················· (2^N)*Rp

·Ts······ 2*R2······················· 2^N
----- = --------···· ----->···· C = -------
Cp*Rp·· (2^N)*Rp··················· 4*R2*Fs

If using the approximation ln(1+x)-ln(1-x) = 2x + 2*(x^3)/3 = 2x*(1 + (x^2)/3) then

····· 2^N···· 1············ 1···· R2········ R2
C = -------*-----· with K = -*(--------)*(--------)
··· 4*R2*Fs 1 + K·········· 3· (2^N)*Rp·· (2^N)*Rp

From the condition (R2/Rp) < (2^N) follows that when using a small input range
(R1 << R2, and thus Rp << R2) that the minimum N must be increased.

regards peter


Post Edited (Peter Verkaik) : 10/20/2007 12:27:46 PM GMT

Rayman
10-20-2007, 11:19 PM
I'm still trying to get a grip on this... I'm currently thinking that the value of the resistor between measured voltage input and C only affects input voltage range and doesn't affect the frequency response at all. This is because it's really the input current that matters and this is the same for a big voltage with big resistor as it is for some small voltage and a small resistor.

Also, I'm think that the RC time on the prop side of C only matters because of imperfections and noise in the quantizer. With larger values of RC, the input pin voltage hovers closer to the Vdd/2 threshold and is more susceptible to noise. On the other side, you can't have RC to small or the voltage there will be often very close to Vdd or Vss and also be susceptible to noise (because a small change in voltage can dramatically change the information stored).

So, I would think you'd want the RC time on the prop side to be a few times the clock period. This way, both the input voltage and feedback voltage can substantially change the capacitor voltage. But, the feedback can keep it away from the Vdd/Vss rails.

So, the one degree of freedom left is absolute value of R (or C) on the prop side. This decides how much current comes out of the Prop output pin. There is a hard upper limit of a few mA. The lower limit is probably also determined by noise. But, more basically, this R determines the R on the input side because we already know the voltage range we want to measure. And, the R on the input side is the input impedance to the ADC. I think this is a more important parameter.

So, here would be the proceedure:
1. Decide on input voltage range to ADC, Vrange.
2. Decide on input impedance to ADC, Zin.
3. Decide on clock frequency of Prop, Fclk.
4. Calculate R1 (prop side) and R2 from Vrange and Zin.
5. Calculate a good C from R1 and Fclk such that R1*C is N times 1/Fclk. (maybe N should be ~8 or so?)

Rayman
10-21-2007, 12:32 AM
I've updated my web calculator and added a new one for the case of added pull-up and pull-down resistors:

http://www.pulsedpower.net/Applets/Electronics/SigmaDeltaADC/SigmaDeltab.html

Tracy Allen
10-21-2007, 12:39 AM
It looks like we are going to need an empirical test to proof the theories!

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Rayman
10-21-2007, 12:58 AM
I'm thinking about trying to directly measure a thermocouple junction voltage. Wouldn't that be neat?

Tracy Allen
10-21-2007, 10:00 AM
Peter, I'm just getting a chance to look at your recent derivation. Thanks for your efforts!

I was initially stuck on the first equation, because I didn't realize that Ut is the voltage at the summing junction and that the components are otherwise the same as in the pdf that you posted about 10 messages back, sigmadeltaadc.pdf (http://forums.parallax.com/attachment.php?attachmentid=49964)? The equation is from KCL. Okay.


Peter Verkaik said...
Here are my latest calculations.
The outcome is indeed different for Fs.

Charge: voltage at outpin = Vdd


Uin Vdd Vdd Ut Ut Ut Ut dUt
--- + --- + --- - -- - -- - -- - -- - 2C*--- = 0
R1 R2 R3 R1 R2 R3 R4 dt




I'm still l puzzled by the steps that use the equation from KCL. Okay, the solution is a decreasing exponential when the outpin is low and an increasing exponential when the outpin is high. Time constant is k=1/RC in either case, and there is an initial condition. But I'm lost on the the significance of the initial condition parameters A and Umin. I need a picture. The shape of that curve is going to be very dependent on how long the output spends high and low and as in the reference cited by deSilva. The initial conditions can change in a complicated pattern. How do the results of these calculations relate to "conversion time"? Changes of Uin are not even considered.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Post Edited (Tracy Allen) : 10/22/2007 3:49:07 AM GMT

Peter Verkaik
10-21-2007, 11:24 AM
Tracy,
I assumed Uin is at the middle of the input range, Uin = (Uinmax+Uinmin)/2
so Ut hoovers around Vdd/2 each Ts.
Then·the generated digital pulses should have pattern ...10101010...
hence the charge/discharge curves.

regards peter

Post Edited (Peter Verkaik) : 10/21/2007 4:59:03 AM GMT

deSilva
10-21-2007, 05:39 PM
(a) There is not really a "static" case: current is flowing all the time between signal source and cap, except in the case of a signal voltage of exactly 1.65 V. To compensate for this, the feed-back pattern is generally very different from 10101, even for a DC signal.
When the signal path draws "Is" through "Rs", the feed-back will deliver "If = 3V/Rf" for as long as it takes to fill-up
the cap again. So:

Is = If*dutycycle

Note that a sequence of 110 110 110 will effectively deliver If/3 per clock, as 0 is not "nothing" but draws the same amount of charge fed before.

However the voltage at the cap will never change for more than:

dU/dt = If/C = 3V/(Rf*C)

per clock tick.

And so there is no dependency on "C" whatsoever, but only on "Rf*C"

(b) This is a DC analysis, what happens for "changing" signals, a sine wave with frequency "fs"?
Well not much else, as the feed-back compensates each rise along the sine wave as soon as it happens, because it is so much faster ("1/clock >> fs")

But what, if it is not? This is part of Peter's analysis: A higher frequency part in the input signal will be noise or even lead to an unstable feed-back. But when starts "higher"?
As a sine changes most at its zero crossover, the worst case input current per time is "2*pi*fs*mean(Is)"

If this can be compensated for during one or a few clock ticks it would be perfect, if not there will be a noticable "instability" of the cap voltage.
The condition is:

If/clock >= 2*pi*fs*mean(Is)

To care already for even the static case, we always need "If >= mean(Is)" so a sufficient condition for a stable operation should be:

1/clock >= 2*pi*fs

Thus an oversampling of 6 wrt to the highest frequeny part should suffice for a stable operation. Unstability will occur when higher frequency parts occur with high ampitiude, the analysis of which is not trivial....

Of course it will improve the worst case situation to put an additional low pass before the delta sigma, but a much more useful device is a second order delta-sigma modulator. I think there is an example for it in the link I gave...

Post Edited (deSilva) : 10/21/2007 9:46:41 AM GMT

Peter Verkaik
10-21-2007, 07:12 PM
Attached is an updated document with component calculations.

DeSilva,
Actually, I am only looking at the situation that the generated pulse
output is ...01010101...
Uin drops out of the equations when I calculate Uripple at the junction node.
Uripple must comply to
Uripple = Vdd/(2^N) where N is the bit resolution

R3 and R4 only have a limited effect on the calculation for C.
But C does depend on Fs, R2·and bit resolution N.

I also found that R2 must comply to
R2/Rp < 2^N where Rp = R1//R2//R3//R4
Usually R2/Rp << 2^N and that's why R3 and R4 have no big effect on the calculated C.
But it does have an effect on allowable input range. (Step 3 in attached document).
Very small input ranges require a larger N if the input range is shifted up or down,
especially beyond Vdd or when Uinmin < 0.

regards peter

deSilva
10-21-2007, 09:04 PM
Peter Verkaik said...
DeSilva,
Actually, I am only looking at the situation that the generated pulse output is ...01010101...


There is never such a situation :) much more often occurs
1111111111
or
00000000

said...
Uripple = Vdd/(2^N) where N is the bit resolution

This should be no surprise, as it is the LEAST POSSIBLE (quantization) noise for a perfect situation


said...
But C does depend on Fs, R2 and bit resolution N.

This is obvious, as you named all degrees of freedom before http://forums.parallax.com/images/smilies/smile.gif

said...

Very small input ranges require a larger N if the input range is shifted up or down,
especially beyond Vdd or when Uinmin < 0.

This is a scaling effect only; the delta-sigma is always oriented towards 0 and Vdd.
Only this range gives the full resolution. When you - say - use just 12.5% of it you have to multiply your N
to get the same resolution again, otherwise you loose 3 bits...

Peter Verkaik
10-21-2007, 11:18 PM
DeSilva,

I don't quite understand your last remark. The minimal required N that follows
from step 3 is to keep the ADC working in its lineair area, not to compensate for lost bits.
Even a small input range has full resolution (0 represents Uinmin, (2^N)-1 represents Uinmax).
This N can also be calculated from R2/Rp < 2^N
If R2/Rp >= 2^N then the voltage at the junction cannot be corrected to Vdd/2.

The physical effect is perhaps clearer from

(Uinmax - Uinmin)/2 > Vdd/(2^N)
which leads to the same minimal N.
In words: Half the input range must be greater than 1 LSB

regards peter

Tracy Allen
10-22-2007, 12:18 AM
Raymond,

It would be neat to measure a thermocouple voltage, however, without amplification it might fall below the noise threshold. Even full scale changes are only on the order of millivolts. Assuming a best case resolution of 14 bits on a full scale span of 3 volts, the least significant bit is 183 microvolts.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

deSilva
10-22-2007, 12:50 AM
Peter, and don't know why I get the impression you have it all upside down http://forums.parallax.com/images/smilies/smile.gif

When designing an ADC you have to Parameters:
(a) The bandwidth "fs" you want to use: You know from Shannon and Nyquest that you have to sample with a clock tqise as high "1/(2*fs)". There is no way out - this is true and basic mathematics.
(b) The resolution (or granularity) of the amplitude. Due to the character of the delta-sigma process you add small and constant packages of charge to hold the balance. So it takes some TIME; when you count time with a clock you need 2^N clocks to guarantee a stable measurement on an equidistant scale. This in fact is CURRENT you measure.
You say: "Ah, in this period T I send P packages of 2 uCoulomb each, so I fed a current of P/T* 2uCoulomb."

As the pin voltage is constant, the current during the "sent-package-time" is determined by the resistor R2. So there is maximum current, issued when you send the maximum of 2^N packages during T.

Now, as you want to catch some dynamic in the signal, you have to adjust T so that it meets the Shannon/ Nyquest condition.

There are complex noise considerations for highly dynamic signals when 2^N is very small; in one posting above I estimated you can run into problems with 2^N<6.

The only important condition is the current equilibrium, which can be expressed through resistor values when the involved voltages are known. The cap then has to be determined by the Nyquist formula.

There is no relation with N to any of them.

Rayman
10-22-2007, 07:30 AM
Tracy: I'm going to change the voltage range using pull-up/down resistors by changing the R1/R2 ratio... But, I admit it might not work. I'm going to try it tomorrow if I have time though (just for fun).

Post Edited (Rayman) : 10/22/2007 12:18:02 PM GMT

Tracy Allen
10-22-2007, 11:41 PM
Rayman,
It will be interesting to see those thermocouple results. The question of the accuracy attainable with the Prop sigma-delta is still open. We already know that the layout makes a terrific difference, and Chip has even suggested which pin combinations are likely to have the best results, based on the interior layout of the mask.
http://forums.parallax.com/showthread.php?p=677970

The range is decreased when the value of R1 (the input resistor) is small relative to R2 (the feedback resistor). There is a question of where to bias the other side of the thermocouple. It could be biased at or near Vdd/2, so that the output would be centered on 50%. Adding a pullup resistor R3=R1 could push the mid-point down to Vss, but it seems to me that that option would upset the balance, in terms of noise coupled from Vdd. Worth a try though.

An external option is to input the thermocouple into a CAZ op amp (e.g. LTC2054), configured with a transistor as a voltage controlled current source with gain to drive the ADC.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Post Edited (Tracy Allen) : 10/22/2007 7:25:29 PM GMT

Rayman
10-23-2007, 02:10 AM
Tracy,

I just got it working! Using R1=100k, R2=390, and using a 1K trim pot to pull up to Vdd, I can read a type-K thermocouple voltage. At least, I get about what I think I should...

My little applet (http://www.pulsedpower.net/Applets/Electronics/SigmaDeltaADC/SigmaDeltab.html) tells me I should get a 12.9 mV range with R1=100k,R2=390, and R3=390.

Basic test was to adjust trim pot so that reading is close to 50%. Then, dipped TC in boiling water to read 18%. Then dipped TC in ice water to read 45%. This is a 27% change...

I looked at a table earlier that said the difference should be 4 mV between 0 and 100 degrees C, which should mean a 31% change. I got a 27% change, which is pretty good (I think) considering how basic this setup is...

Of course, you'd need a look-up table to convert to actual temperature...

Tracy Allen
10-23-2007, 03:22 AM
That's encouraging! Whatever the DC stability may turn out to be, it shows that one can detect millivolt level changes. What is the hardware setup, I mean, what board layout and pins, and where is the other side of the TC connected?



Nice applet by the way. (note to other readers: R1 and R2 designations in the applet are reversed from the ones in Peter's PDF)

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Rayman
10-23-2007, 03:28 AM
Here's a photo of the test setup:

(you can see both ends of the ~1 meter long Type-K thermocouple wire in the photo...)

labsmoke
10-29-2007, 03:34 AM
Im just getting started on·the ADC part for my·"rigg from hell"...

On my debug screen i just get the same value whatever i do...

@12 bits samplin rate i get "2200-3000" values on the screen going up and down in a fairly slow rate not in anyway linked to the voltage im sending in, im using the standard ADC Appnote hookup to the prop.


Any thoughts?

Rayman
10-29-2007, 09:59 AM
If you have a VGA setup, try my code:

http://www.rayslogic.com/propeller/Programming/ADC.htm

and see if it gives the same answer...

labsmoke
10-29-2007, 03:18 PM
rayman:

I have some trouble sorting out what part of your code that does the analog converstion, its not really the smallest of codes, dont you have something thats not 4000 longs? hehe...

Rayman
10-29-2007, 05:59 PM
It's just the "Dual_ADC1.SPIN" object that does the conversion. The rest is just GUI...

labsmoke
10-29-2007, 10:13 PM
oh, i see...ok it looks fairly simple, ill give it a try...

Rayman
10-29-2007, 11:07 PM
Of course, you should check out the Microphone2VGA example and the counters Appnote, if you haven't already...

rjo_
10-30-2007, 02:51 AM
I love this thread... I've been in and out, so I haven't had time to really study it... But the flow and the content are beautiful.

Before I say anything about the content... I would like to empathize with the experts a little. I still remember how it feels to have patients ask me all of the right questions and then come to exactly the wrong conclusion... and then behave as if they were right an I was wrong.

This thread is related to a brief conversation that I had with deSilva about an MIT Professor who claimed that Ohm's law should no longer be considered to be a law.

deSilva was correct (of course) in basically saying that laws are abstractions based upon idealized circumstances, which almost never really exist. And that the point of an engineering education was to learn this fact and then learn how to live with it.

The issue comes home for the amateur the first time he tries to actually do something with the laws he has been studying... and the Resistor/Capacitor circuits are a great way to illustrate the issues.

I wanted to make a simple Ohm meter. I basically followed the Lab session.... and the data was a complete mess. (I think) because I was using various kinds of resistors... and because obviously with some of the resistors... the more I measured them... the more they heated up... and the more they heated up the more they resisted... and the longer the time to threshold became.

So, unless you take temperature into account, which I didn't see in any of the formulae (on very brief inspection)... then the formulae will only work if you have a circuit that forces heat to be constant.... THAT"S an opinion... and I am prepared to be wrong.

Rich

Mike Green
10-30-2007, 03:30 AM
Rich,
Most of the time, when working with resistors, you assume (and choose your circuit and resistors so) that the current through them is small enough so there's not much self-heating and the resistance is dependent (practically speaking) only on ambient temperature which is presumed to be reasonable (since we normally have to live there). In a sense, the temperature is taken into account in the underlying design so that the circuit operation is minimally dependent on it. In "the old days" when most resistors were 20% tolerance and capacitors were +200/-50% tolerance, you really had to design your circuits to tolerate wide variations in values. Now when most resistors come in 5% values and 1% values don't go for an outrageous premium, you can use other designs that were impractical before.

Rayman
10-30-2007, 03:43 AM
Once you've had a few 2W resistors explode in your face, like I have, you become very aware of resistor wattage rating and heating effects...

Mike Green
10-30-2007, 03:56 AM
rjo_,
There's a real trick to listening to people, understanding how they came to the conclusions they did, particularly accepting their underlying experiences, and reframing their experiences in terms of "how the world really works" whatever that may be at the moment while leaving wiggle room for new (real!) understandings of "how the world really works" that seem to emerge these days almost hourly ... and not looking like a fool in the process.

Rayman
10-30-2007, 06:40 AM
rjo_,

Let me expand a bit...· First, some people (like myself) may fail to mention the need for proper wattage selection of resitors, just because it's second nature for us.

Second, if you really need more precision, check out the resistors here:

·http://www.caddock.com/

They have laser trimmed resistors and dividers with virtually no thermal, voltage dependence...

deSilva
10-30-2007, 06:58 AM
As Mike said: Nowadays we can realize designs by high precision parts, formerly impossible. My pet example is Babage's Analytic Engine, wihich was NOT possible to build 200 years ago due to the slopyness of the mechanicists of that time and their insuffient tools....

Precision resistors are the basis for precision ADCs and DACs.
A "general" circuit however works differently. This only came to my mind after having viewed 15 minutes of Prof. Levien's lecture RJO_ was refering to. All electronics of the past (and most of the future) only worked because resistors are PTCs by nature. This gives them a negative feed back characteristic in case of current fluctations.

I doubt that many circuits will ever have worked if we had the bad luck of NTCs only in our toolbox http://forums.parallax.com/images/smilies/smile.gif

Tracy Allen
10-31-2007, 01:52 AM
Integrated DACs and ADCs depend not so much on precision resistor (or capacitor) values per se, but on precision ratios of them that can be most easily obtained by integrated circuit technology.

These days 0.1% surface mount 0805 and 0603 resistors are available off the shelf at good prices from major distributors. That has been a real boon for making precision analog circuits that don't require trimming, or to reduce the trimming to a minimum. That level of precision is a good bet for something like this sigma-delta circuit, like the thermocouple circuit with offset to zero that Rayman demonstrated.

There is still a question in my mind about characterization of drift of the Propeller threshold voltage with time and temperature. What effect will that have on precision sigma-delta readings?

Also available are 5% and better surface mount film capacitors that have excellent characteristics for sample and hold and high frequency analog circuits. And low-K ceramics are built with ever better materials that cram more capacitance into smaller packages. We haven't discussed what type of capacitor would be best for delta-sigma. Intuitively, it should be one with low soakage factor, and low ESR and generally good high frequency characteristics.

I'm not sure, did we resolve the question of how to choose the capacitor value? I am still not convinced that there is a first order bandwidth restriction introduced by the RC time constants at the input, and still am of the handwaving opinion that the optimum is wide and is mostly dictated by noise considerations.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Tracy Allen
www.emesystems.com (http://www.emesystems.com)

Rayman
10-31-2007, 02:54 AM
Tracy Allen said...

I'm not sure, did we resolve the question of how to choose the capacitor value? I am still not convinced that there is a first order bandwidth restriction introduced by the RC time constants at the input, and still am of the handwaving opinion that the optimum is wide and is mostly dictated by noise considerations.




· I don't know the answer for C either.· Fortunately, most of the things I'm interested in right now are slow.· For DC signals, it doesn't appear to matter what you use for C...

Drone
12-22-2007, 08:24 PM
Rayman & Slosjo,

There a pair of nice delta-sigma ADC calculator applets at www.pulsedpower.net (http://www.pulsedpower.net), look under Applet Index > Electronics. If anything, they may be useful for checking your component calculations.

David

Rayman
12-22-2007, 09:17 PM
Wait a minute... Hey, that's my Applet! (Actually, that's my website too :)

Drone
12-22-2007, 09:39 PM
So right you are Rayman.. I forgot you spawned that gem! Sorry - Daivd

deSilva
12-22-2007, 11:02 PM
@Drone,
did you ever wonder why there is no "C" calculated in that applet?
What Ray posted is the well known situation.

What we ask ourselfs is, whether the RC combination really acts as a low pass filter to be designed according to aliasing considerations, or whether the high frequency feed-back will shift all that into higher areas of "noise".
It will do no harm to take "Nyquist conforming" values for C, however experience shows that is does not seem to matter...