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Skogsgurra
09-16-2007, 12:03 PM
I haven't read all 615 posts in the·"What do you want more of.." thread. So, this may have been covered before. Anyhow. It is something that may need to be discussed in a separate thread. Like this.

There are many applications where less would be more. A small, say DIP18, package is sometimes all you need and it would make a great peripheral processor. (BTW, that's how the·PIC processors started. They were just that - Peripheral Interface Computers - for the CA systems).

An 18 pin package would give you a full byte of GPIO plus the EEPROM, USB, XTL, BOEN, RESET·and Power connections. I am not so sure about the XTL, the RC clock would be OK for bit-banging and simple one-wire interfacing.·Which would make a DIP16 the natural choice. Do we always need the RESET and BOEN? Without them, and with the RC clock, we could have 12 GPIO in a DIP18.

Has this been discussed? Would it be a reasonable addition to the family? Thoughts?

Edit: Corrected "Peripheral Interface Computers"

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Post Edited (Skogsgurra) : 9/16/2007 5:19:11 AM GMT

deSilva
09-16-2007, 03:00 PM
Most (all?) manufacturers of microcontrollers give you a "family", positioned in a 4D-matrix:
Cost, Performance, (Program-) Memory, Pins
Note those parameters are tightly coupled.

Parallax has trickily avoided the Program-Memory dimension by using an external EEPROM as well as by the bottle neck of the HUB RAM. On the other hand there is the option of a much wider performance scope than with most other architectures, where the choice is rarely more but: 8 Mhz Lowpower / 12 MHz standard / 20 MHz advanced, "tiny" or "mega" instruction set http://forums.parallax.com/images/smilies/smile.gif

So what one could wish for is
- low pin-out (for reduced real estate)
- low power (4 COGs, for reduced price)
- low price as such (whatever best suited; don't say: "Just buy 10,000")

deSilva
09-16-2007, 03:07 PM
The SpinStamp is exactly the thing a needed (28p, eeprom, crystal, regulators on board). The price tag however is prohibitive...

Skogsgurra
09-16-2007, 03:17 PM
I forgot to say that by QuarterProp, I meant two cogs. But keep the hub ram as is.

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BradC
09-16-2007, 03:38 PM
Actually, I kinda like the sound of that.

Even a "half-prop" would be useful, or maybe just the standard core with only a limited number of pins bonded.

Having said that, it kinda dilutes the per-device quantities and I'd guess would reduce the profit margins on the ultimate end products.

My ideal proto-tool used to be the PIC 16C876. 28 pin skinny dip. Never took up a lot of space, easy to work with and had enough IO for pretty much anything I used to do.
I'd have no problems paying current prop prices for a form factor like that, even given the need to supply external program memory.

I guess I just need to gear up for SMD work and make my own boards. That'd take a lot of the sting out of it as-is.

deSilva
09-16-2007, 03:46 PM
I am also interested in a "cost break-down"; ultra fast static RAM is not cheap...

32KB HUB RAM: ?
COG (x8): ?

HUB-Logic: ?
32KB ROM: ?
Pin-Out (40p DIP): ?

ErNa
09-16-2007, 09:25 PM
Just an idea:
it is often stated, that more cog ram makes no sense due to limited 9 Bit adresses. But, this is only true for immediate access, addressing via registers in the "normal" cog memory gives access to as much memory, as is available. A two level pointer structure wouldn't event limit the number of pointers, a single long in normal cog memory could hold the address of the first pointer in the expanded memory.
Such an solution should be great!

deSilva
09-16-2007, 09:51 PM
Well, ErNa, this a totally new concept. At the moment there is no such thing as an "addressing via registers". Addressing is ALWAYS done by a 9-bit pointer inside the instruction, which is limited to 9 bits.

scotta
09-16-2007, 10:10 PM
It would be nice to see a sub $6 dollar chip. This would allow
me to replace my asic library with propellers. This would go
over even better if they had a rom inside. Given I know they
are going to concentrate on bigger fish first.

Scott

Fred Hawkins
09-16-2007, 11:58 PM
In the other direction, a $20 (in quantity, who-knows? single piece) chip: http://www.intellasys.net/tools/WP_EmbMicro.pdf

(Chuck Moore's latest adventure in chipmaking; article does offer some basis upon which the propeller should be critiqued -- intercog communication and memory issues. See page 4, which does seem to be directed right here.)

Post Edited (Fred Hawkins) : 9/16/2007 4:04:47 PM GMT

deSilva
09-17-2007, 12:16 AM
Thanks for the link - astonishingly naive, but on a niveau management can understand.
He seems mostly concerned with dataflow issues, which - as we have learnt - can be a bottleneck...

High end DSPs (Shark, Blackfin,...) however still play in another league than the Prop...

Skogsgurra
09-17-2007, 12:32 AM
Very interesting article! Thanks!

It clarifies the huge difference between us bitbangers and you multimedia guys. We are happy if we can have a set of very fast processors and if we can get predictable performance. The memory acess is not an issue in most such applications. I think that the length of you-know-which thread is a result of that difference being poorly understood. The Prop (to me) is a mean bitbanging machine with some AV capability. And that is just fine (still my view).

The last part of the article mentions FORTH as a native machine language. Harris had a chip (the RTX 2000) that was based on that. It was a very clean design. And it packed up to four (IIRR) instructions in a 16 bit word. I won a design contest on that machine. It was very nice to use, but somewhat unstable (I think it was the development system, actually). I still have it in the attic. It did cost around USD 3000 at that time. Anyone interested? http://forums.parallax.com/images/smilies/smile.gif

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deSilva
09-17-2007, 12:38 AM
Well this thread now goes again into the high-end regions. Let's come back to the $3 market http://forums.parallax.com/images/smilies/smile.gif

Graham Stabler
09-17-2007, 01:53 AM
I've lost track of the big thread but I seem to remember that Chip said they were working towards bigger rather than smaller.

Ditto on the propstamp, would be useful for lots of things but is too expensive (very possibly with good reason).

Graham

Chad George
09-17-2007, 02:27 AM
I totally agree with this idea. I mean every design I've made with the prop I've run out of pins so I'm totally for a bigger prop2. But the other end of the spectrum would solve the problem too.

Even just 12 IO lines would be awesome if it was in a cheap/small package. Why bother changing anything. I'm definitely grasping here, but how possible would it be to take the current design and package it into a smaller pin count design with just leaving the unused pins not connected (hopefully they'd still be available from cog-to-cog communications)

I know resources are limited and need to be put where they reap the most benefit, but this would definitely be a huge plus to the propeller product line IMHO.

-Chad

Graham Stabler
09-17-2007, 02:41 AM
I must admit it does sound like a sort of cut and paste job on the layout for a smaller version.

CJ
09-17-2007, 02:52 AM
I am pretty sure I read somewhere here that the prop has little room to spare in the QFN package as it is now.

and the cogs take up almost exactly half of the current die area, with the hub taking the rest(wish I could locate the die layout picture that was posted awhile back)

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Fred Hawkins
09-17-2007, 03:21 AM
Skogsgurra said...
Very interesting article! Thanks!

It clarifies the huge difference between us bitbangers and you multimedia guys. We are happy if we can have a set of very fast processors and if we can get predictable performance. The memory acess is not an issue in most such applications. I think that the length of you-know-which thread is a result of that difference being poorly understood. The Prop (to me) is a mean bitbanging machine with some AV capability. And that is just fine (still my view).

The last part of the article mentions FORTH as a native machine language. Harris had a chip (the RTX 2000) that was based on that. It was a very clean design. And it packed up to four (IIRR) instructions in a 16 bit word. I won a design contest on that machine. It was very nice to use, but somewhat unstable (I think it was the development system, actually). I still have it in the attic. It did cost around USD 3000 at that time. Anyone interested? http://forums.parallax.com/images/smilies/smile.gif


Yes, I'd be interested. It's, I think, Moore's second chip licensed to Harris. Harris hardened them against xrays and such.·They apparently·sold many to NASA for stuff that went far away.

MarkS
09-17-2007, 03:47 AM
I'd much rather see a Prop with 8 or more cogs, but with the inclusion of a few Prop-to-Prop communication pins and associated software functions and protocols. I was also thinking about the Prop II's reported 64 IO pins. I was wondering how hard it would be to add a pin to the chip that, if held high, turned half of the IO pins to address (24-bit)/data bus (8-bit) pins and if held low or left floating, left them as IO pins?

Ah.. A man can dream...

Gadgetman
09-17-2007, 05:13 AM
I can see the use for 2 or 4 COG chips with limited number of I/O-pins.

A 2COG would be easy to use as a 'buffering protocol changer', going between RS232/SPI/I2C and so on...
It could also be used for datalogging and transmitting, without the need to stop logging while doing the transmission. With 8 I/O-pins it should be possible to get it into a 16 or 18 pin package.

While a 2COG chip may be able to generate a Video signal, it doesn't have much 'spare' capacity to do image processing, a 4COG would make a decent 'graphics subsystem' Stick it with 16 I/O-pins and it should fit into a 24pin package. IT should also work well as a general sub-processor, network hub(serial or whatever), datalogging with interpretation. Of course, this probably won't be much cheaper or smaller than the normal 8COG model, so the economic viability is rather low.

Then there's the question of COG/HUB timing. Should the Round-robin HUB-access scheme be adapted so that the slots come more often, or should it be kept at the same 'access every 16 clock ticks' pace to keep compatibility with existing code?

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hippy
09-17-2007, 10:49 AM
Gadgetman said...
Then there's the question of COG/HUB timing. Should the Round-robin HUB-access scheme be adapted so that the slots come more often, or should it be kept at the same 'access every 16 clock ticks' pace to keep compatibility with existing code?


Without conditional compilation or, better still, ability to determine type of chip being executed upon, differences will cause a nightmare for object re-use and in porting code prototyped on a larger chip ( using on-chip logic analysers, VGA/TV for debugging and other gizmo's ) to a smaller one.

I think any debate on scaling-down is as difficult as that on scaling up. Some people will want huge processing power but need few pins, others will need more pins but not so much processing power. My pragmatic approach would be; same as what we have, just less pins connecting to silicon die. Drop BOE, just one power pin etc, yes, but otherwise 'the same insides'

The same too for any 'fancy improvements'; across the board or not at all.

Apart from the debate on how many legged variants, the lack of variants is one of the big advantages I see.