Tumbleweed
01-25-2007, 09:12 AM
Hey All,
Has anyone out there ever used a single BSII chip to link to·4·'daughter' BSII chips to expand the number of IO lines available?
For example:
Master Chip IO line 1 connected to Daughter Chip 1 Input pin.
Master Chip IO line·2 connected to Daughter Chip·2 Input pin.
Master Chip IO line·3 connected to Daughter Chip·3 Input pin.
Master Chip IO line·4 connected to Daughter Chip·4 Input pin.
Daughter Chip 1 IO Line 1-8 connected to Device 1-8
Daughter Chip·2 IO Line 1-8 connected to Device 9-16
Daughter Chip·3 IO Line 1-8 connected to Device 17-24
Daughter Chip·4 IO Line 1-8 connected to Device 24-36
My goal is to decentralize the workload (to increase speed and address more than the available IO pins on a single chip) and communicate directly with one chip via my PC computer that will tell all the other chips what to do.
Thanks,
Lance
Has anyone out there ever used a single BSII chip to link to·4·'daughter' BSII chips to expand the number of IO lines available?
For example:
Master Chip IO line 1 connected to Daughter Chip 1 Input pin.
Master Chip IO line·2 connected to Daughter Chip·2 Input pin.
Master Chip IO line·3 connected to Daughter Chip·3 Input pin.
Master Chip IO line·4 connected to Daughter Chip·4 Input pin.
Daughter Chip 1 IO Line 1-8 connected to Device 1-8
Daughter Chip·2 IO Line 1-8 connected to Device 9-16
Daughter Chip·3 IO Line 1-8 connected to Device 17-24
Daughter Chip·4 IO Line 1-8 connected to Device 24-36
My goal is to decentralize the workload (to increase speed and address more than the available IO pins on a single chip) and communicate directly with one chip via my PC computer that will tell all the other chips what to do.
Thanks,
Lance