Question on shift register

[metron9]

As I said in another post, I was going to play with shift registers and I setteles on the CD74HC164E
http://www.datasheetcatalog.com/datasheets_pdf/C/D/7/4/CD74HC164E.shtml

The datasheet is not totally clear to me so please correct my assumptions below

Q0 theu Q7 output

CP clock line
MR resets all to low
VCC and GND or course

Here is where I think I understand it

DS1 and DS2

Use either one for data input but set the other one to logic HIGH to enable the shift register

I see using the shiftout command in the basic stamp (I have leds on outputs) that it works but when the data is shifted into the device all of the output lines get a short high pulse of about 60uS. I understand if the number is 128 for example, the first bit shifted out is a 1, so Q0 is set high aparantly for the time it takes the clock to shift the next bit in, a number of 254 would have Q0 high for 60 * 7 uS during the shifting in.


By making the non dataline DS1 or DS2 LOW while the shift in nothing gets shifted in so it must be held high for the shift register to take data.
Is there a way to eliminate this short pulse on outputs that will be 0 during the shift in of data?

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Think outside the BOX!

[Chris Savage]

Do you already have the 164's?· If not, using the 74HC595 is much simpler and we have tons of code and documentation examples.· Just a thought.

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Chris Savage
Parallax Tech Support

[metron9]

Yes I do have some I added some on my last digikey order, I usually try and order a few devices i have not used in any projects just to play with and get to know.

The question is really just is this the normal operation of this specific device or is there something I am missing. I would imagine a typical use of this device would be to send the serial data and when it is complete signal the device that is actually reading the parallel data that the data is ready, or the device receiving would wait for a minimum time on for all bits but that seems like a waist of clock cycles.

I will read about the other device and usage to get a better idea how a receiving device receives the parallel data on the output pins.

Remember i just hook things up and try and follow the datasheet, like I say it works but the 60uS blink is something I did not expect to see.

I thought it would work similar to using 8 stamp pins where you could change all pins to high or low at the same time, I thought you could send the 8 bits and when the 8th bit was in all bits would reflect the new 8 bit number, this would require the device to have an internal buffer and logic to swap the buffer with the output pins on the falling edge of the last clock cycle.

So just learning the in's and out's of devices i have never used as I think of designs in the future I may say hey i could use a shift register here, that of course requires you to know that they exist.

EDIT>>> Ahhh I see i just read the datasheet (front page) of the 595 it has a buffer and can transfer all 8 bits at one time.

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Think outside the BOX!

Post Edited (metron9) : 9/20/2006 4:37:29 PM GMT

[matthelm]

This is how the '164 works. The '595 has an output latch, so you don't see the data shifting in. (ie a buffer between the shifted data out, and the output of the chip)

Don't feel bad about this. I had an EE that should have know better try to use the '164!

[Chris Savage]

Okay, now I see what you mean, but you already figured it out.· The lack of a latch, which the '595 has.· I prefer the '595 for obvious reasons, but it can also handle more current than 8 I/O pins...Also, adding more 74HC595's doesn't take any more pins.

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Chris Savage
Parallax Tech Support