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ManAtWork
03-17-2012, 04:03 PM
Hi,

I'd like to connect a 24 bit dual channel sigma-delta audio ADC like the PCM1803A to the propeller. It think it should be able to directly read the serial bit stream from the ADC using bit banging. But the ADC needs a strange clock frequency of 24.576MHz (256 times the sampling frequency of 96kHz). It should also be no problem generating this with one of the propeller's PLL timers. But I found no specs about the jitter of the PLL output. This is critical to the performance of a sigma delta converter. I'd like to achive 90dB SNR or 15 usable bits. Do you think this is possible? Has anybody already done this?

darreno
03-17-2012, 06:12 PM
The PLL won't introduce much jitter but the fractional divider use to get your 24.576 frequency will have measurable jitter. I'm not sure if this will help but it explains the jitter caused by dividers. I'm in the process of digesting it now and so far it has helped me.

www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

If this is a dedicated circuit you could buy a 6.144Mhz crystal then you'd have a nice clean clock for the ADC. Those crystals are also used in SPDIF applications.

Leon
03-17-2012, 06:24 PM
24.576 MHz is a standard frequency for crystals, they are available everywhere.

darreno
03-17-2012, 09:01 PM
6.144 gives you the option of running the cores are more than one frequency using the PLL. Mouser seems to have tons and ebay too.

ManAtWork
03-19-2012, 09:07 AM
Thanks for the suggestions. If I run a propeller from a 6.144 crystal, I'd have the choice to run it at x8 or x16 clock which gives 49.152 or 98.304MHz. 98MHz is out of spec. Although I heard that many people have successfully overclocked the propeller at 96MHz I don't want to because it's an industrial application which should run as reliable as possible. 49MHz is a bit low but should be sufficient. The ADC outputs the bitstream at a rate of 64 bits per sampling period or 6.144 bps (2 x 24 bits plus sync). So I have two assembler command cycles (8 system clocks) per bit. Enough for a TEST and a ROL instruction.

I'll try it out. I can later change the crystal against a 5MHz one and look if it makes a difference using an "odd" PLL factor.

evanh
03-19-2012, 01:09 PM
You don't have to feed it an exact frequency unless you are wanting it as a portable source without resampling ... but I figure that's exactly what you are wanting.

I'd probably have it with it's own crystal for the sampling and do the serial bus clocking separately from the prop. Prop would be the master and the pcm1803 the slave.

ManAtWork
03-19-2012, 01:51 PM
I don't need compatibility to any audio format. The reason I want an exact sampling frequency of 48 or 96kHz is that I have a power circuit with a switching frequency of 24kHz near it. A sample frequency that is a multiple of this cancels out switching noise I hope. A PLL running out of an NCO timer would have the advantage that I can lock ecactly to that external frequency even if it is not exactly 24kHz. I have to try out if this is really necessary.

Yes you are right, running the PCM1803 as slave would allow synchronisation of the serial bitsteam to another clock. But I doubt that it would be of any advantage. I have no cycles left for toggling the bus clock via software. If the sampling clock and bus clock are synchronous the chance of adding noise is minimized.

darreno
03-19-2012, 10:23 PM
The PLL will run at 6.144MHz x16 or 98.3Mhz but the ADC would be running at 6.144MHz x4 to get the 24.576MHz for the ADC. Are you mixing up 98.3Mhz with 96KHz? Since only powers of two are involved you'll get a fairly stable clock for the ADC.

I'm curious, why did you chose a 24bit ADC?

ManAtWork
03-20-2012, 08:21 AM
No, I don't mix it up. Actually there are two PLLs. One to generate the system clock for the propeller, one to generate the ADC clock. I'll use a 6.144MHz crystal. The propeller will run at 49.152MHz (x8 PLL mode). The ADC will run at 24.576MHz master clock (generated by a timer PLL and output at an I/O-Pin of the propeller). This is divided by 256 or 512 by the ADC to derive the sampling clock (48 or 96kHz). The clock will be neary jitter free. But I could also use a different crystal frequency, say 5MHz. In this case the PLL output won't be jitter free because the NCO feeding the PLL has an odd division factor (FRQx value).

I've chossen a 24bit audio ADC because...
a) it's cheap (~1.5$)
b) it has integrated filters that have very good stop-band supression (better 100dB for multiples of the sampling frequency)
SAR ADCs always have the problem that you can catch a HF spike with the S/H input.
c) I don't have to care about gain or offset errors because I only have to make relative measurements. So I don't need absolute acuracy but good linearity.

It's an experiment and I'm still not sure if it works. But if it does I could replace a very expensive circuit of around $100 with a propeller and some small parts for less than $10.

Mark_T
03-20-2012, 12:36 PM
I have code for driving a WM8783GED (another cheap 24bit I2S audio ADC) if that might be of interest... IIRC I use a 6.144MHz crystal and overclock to 98MHz. I use 8 instructions per bit read, but 4 of them are NOPs, so it ought to work at half the clock rate.

ManAtWork
03-20-2012, 03:45 PM
:lol: Haha, this WM8782 is really a good example of a "reduced to absolute minimum" thing. It has a 8 pin package, not even a pin left for BCLK, no reference bypass cap, no separate ANGD and DGND pins... and even cheaper than the PCM1803 (or its "pin saving" version PCM1807). But as expected, THD and stop-band suppression are 20dB worse.

darreno
03-20-2012, 04:08 PM
Sorry, I misunderstood you about the 98MHz. Now I realize you were referring to the propeller being out of spec.
I haven't read about anyone having problems running at 100MHz but you may want to stick to 8x if it's for a commercial product.

Parallax sells a 6.25MHz crystal is their online store, the description says it's reliable but I'm not sure if it's officially supported.