View Full Version : Is it recommended to have a capacitor on the VDD of the EEPROM?

Don M
11-11-2011, 12:48 AM
I was thinking I read somewhere that it is suggested to have one. In my design I'll have the EEPROM close by to the Prop and have 4 .1uF bypass caps around the Prop. Should I add a 1uF to the EEPROM also? A .1uF or both?

11-11-2011, 12:53 AM
When I was a kid I got all my parts from old mainframe computers (worth millions in their day) and I noticed that every chip had its own 0.1uF capacitor, plus at the end of a row of chips (eg every 10 chips) there was a 10uF tantalum.

Now, that was old-school TTL, but I've got in the habit of using a 0.1uF for each chip. So I put one one on the eeprom, and one on the ft232 etc etc. Maybe I end up using more 0.1uF caps than necessary, but they really are so cheap that I don't think it matters.

Phil Pilgrim (PhiPi)
11-11-2011, 02:39 AM
If the EEPROM's Vdd pin is proximal to one of the Prop's, there's nothing wrong with sharing bypass caps. The idea is to create a low-impedance (at high frequencies), distributed power "blanket" across the PCB, with the lowest-impedance points nearest the ICs' power connections. That's what the bypass caps attempt to accomplish.


11-11-2011, 04:47 PM
So, does the EEPROM qualify as high-frequency in this context?

Phil Pilgrim (PhiPi)
11-11-2011, 04:51 PM
A 1 Hz signal qualifies as high frequency if the rise and fall times are short enough, so yes.


11-11-2011, 05:13 PM
It is good to have a .1uF ceramic capacitor on each chip and across each connector where power
leaves the board. You should also use 10 to 47uF tantalum cap around the board in several places
on each power supply rail.

This is called distributed capacitance and it makes for solid design in high volume production.
The idea is when a chip needs to draw allot of current, say several outputs go high at once. There
is capacitor close by to supply the initial current. Then after the outputs change state the current
comes from the power supply bus.