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View Full Version : Prop II info from the Webinar...



Cluso99
10-28-2011, 06:37 AM
The webinar finished 30 mins ago, with Chip's presentation the last. I understand the webinar will be posted but it is after 10pm at Parallax.

Here is what I recall...

It has been quite a learning curve with the layout. There are about 40,000 flip-flops in the Prop II. There were about 160*8=1280 in Prop I.

After the original chip layout simulation the critical path was showing only about 80MHz clocking. Chip has now refined the critical paths and it now looks like 180MHz.

There will be ~126KB Hub SRAM and ~2KB Hub ROM.
128 pins in QFP 14mm?
92 General purpose I/O
8 Cogs
64bit CNT register
Video will clock at ~230MHz
Maybe ~$12-$15 at launch
180nm

Expect the instruction set info to be posted on the forum shortly.

If the prop were done in 45nm then perhaps it would clock at 1GHz, have 2MB hub ram and 16 or 24 cogs. But this would require ~$1M+ for prototype layout costs vs ~$160K for 180nm. Anyone with a spare $1M ??? Could be some super ROI (return on investement) if you do! This could give the ARM a run for its money hey.

Perhaps we should start an account for Parallax to buy tickets in the lotto ;)

william chan
10-28-2011, 06:47 AM
Video will clock at ~230MHz

The Video runs on a separate clock?

Cluso99
10-28-2011, 06:53 AM
Video runs on a separate clock now, via PLL. Guess it will be the same concept but allowing a higher output than now.

Just remembered...

Each counter is able to do 2 PWM outputs. There is a lot of additional functions in the counters (understatement).

16x16 multiply in 1 clock; 32x32 multiply in 16 clocks; 32/16 divide in 16 clocks; Cordic ? clocks.

User Name
10-28-2011, 08:29 AM
Thanks for posting this, Cluso. I had every intention of "tuning in" the webinar but got lost in other activities.

Prop II is looking pretty exciting!

180 nm works for me. I also like the projected introductory price. Kudos to Chip and Co.

Baggers
10-28-2011, 09:56 AM
Thanks for the post Cluso :D, great news, and a great price for what is/will be a great chip!
Now where was that $1m+ I had laying around?... if only! cos it would be worth it!

jmg
10-28-2011, 10:46 AM
Each counter is able to do 2 PWM outputs. There is a lot of additional functions in the counters (understatement).


and also Two quadrature counting channels.
Less clear on Capture, and overflow handling features ?
I hope more complete info on the counters goes up soon, so we can check they have not missed anything.

Being able to run the core slower than the Counters, would be nice for power saving.
With simple gate and steering done the right way, you can create a Auto-ranging reciprocal Frequency counter with two 32 bit counters,
with a common capture enable ( SW SFR flag AND with Edge ), and a CaptDone flag.

Such counters have very wide dynamic range (Hz to 10's MHz), with a fixed digits/second precision, so would make an ideal Obex..

32 bits is smallish these days, so a system like on the System counter of reading > 32 bits would give Prop 2 and edge.

Rayman
10-28-2011, 11:30 AM
Thanks Cluso. I missed it too...

Any update on timeline? (I'm guessing 6 months).

Cluso99
10-28-2011, 11:48 AM
There was no timeline. My guess would be min 6 months (no inside info)

i recall Chip saying that the video can be loaded and another load can be done without having to do a waitvid - meaning you can have a waiting set loaded in advance. Video can be 1080p.

These counters are really going to be fantastic, along with the I/O pins.

No guarantees with first iteration that the fuses will work, nor code decryption. Neither for intracog high speed comms (between chips).



Wish I had a spare $1M :) There are not many certainties, but this would have to be one with great prospects!

David Betz
10-28-2011, 02:30 PM
If the prop were done in 45nm then perhaps it would clock at 1GHz, have 2MB hub ram and 16 or 24 cogs. But this would require ~$1M+ for prototype layout costs vs ~$160K for 180nm. Anyone with a spare $1M ??? Could be some super ROI (return on investement) if you do! This could give the ARM a run for its money hey.

Perhaps we should start an account for Parallax to buy tickets in the lotto ;)

That $1M sounds cheap compared to what I thought Chip said. Didn't he say more like $3M? I guess it doesn't matter one way or the other if they win the lottery though. :-)

tonyp12
10-28-2011, 03:01 PM
"90 nm process refers to the level of CMOS process technology that was reached in the 2002–2003 timeframe"

How about 90nm then, $500k (guessing) should not be hard to come up with.

12cogs
360mhz
512k sram, 32k rom

But maybe it's other technical issues arises when going smaller and Chip have to start from scratch.

Oldbitcollector (Jeff)
10-28-2011, 07:00 PM
Most excellent! I had trouble connecting to the live event last night, so I'm looking forward to the "tape delay" version. :)

Thanks for posting that!

OBC

Oldbitcollector (Jeff)
10-28-2011, 07:02 PM
If the prop were done in 45nm then perhaps it would clock at 1GHz, have 2MB hub ram and 16 or 24 cogs. But this would require ~$1M+ for prototype layout costs vs ~$160K for 180nm. Anyone with a spare $1M ??? Could be some super ROI (return on investement) if you do! This could give the ARM a run for its money hey.



Will they take a check? ;)

Ken Gracey
10-28-2011, 07:27 PM
To clarify the numbers Chip mentioned, the current Propeller 2 design process is 180 nm. The test chip shuttle runs and first production lot are in excess of $500K but around $1M by the time we've got our characterization, package startup and early documentation efforts completed. The 45 nm process would support 1GHz per cog but would cost in excess of $3M (unverified, at least by me) of manufacturing costs. Indeed, the costs for designing and producing chips are very high.

Ken Gracey

__red__
10-28-2011, 08:36 PM
I wonder how much of that cost is "tooling" verses the cost of the actual devices. IE, with a $3m cost - what would the cost per device be when it hit market.

I'm REALLY excited because I think the P2 may hit a price/performance point that will beat both GPU and FPGA arrays in my application.

Cluso99
10-28-2011, 09:13 PM
Thanks for the clarification costs Ken. I did think Chips prices sounded cheap. Of course none of that includes the man-years development costs and the hardware and software that has been bought along the way.

If I win the lotto I would gladly sponsor the P3 (45nm version). And I don't think I would be the only one! IMHO the P3 would be an ARM killer for ipad clones and phones so long as the power consumption could be controlled. Nice to dream anyway ;)

Ken: (OT) WOuld it be possible to get some sort of lower level block diagram of the counter logic (inc video logic) in the existing prop? I don't believe we have touched the surface of what these counters could be made to do, if only we just had more low-level info. I don't want to take Chip or Beau away from the PropII - could an FAE delve into this perhaps?

Rayman
10-28-2011, 09:37 PM
Marketing idea: Maybe they could use some of those fuses to disable 6 cogs and sell a cheaper, 2 cog version...

JRetSapDoog
10-28-2011, 09:42 PM
Regarding a release timeframe, when asked about this, Chip safely stated that he didn't know. However, he indicated that there was maybe 8 weeks of addtional integration work (my words due to poor memory), and then that there'd probably be at least 2 iterations of testing (maybe that means at least one shuttle or sample run) before production could begin in earnest. He also said something to the effect that the integration work (my words again) and/or coordination with the synthesis team were proceding particularly well recently and, paraphrasing, picking up steam. Given all that, I'd guess that the above estimate of a minimum of six months is accurate since it's difficult to imagine how required test runs and testing could get done any faster. Also, if memory serves from reading this forum, there seems to be a foundry lead time of at least two to three months to enter mass production. Hope that helps shed light on the timeframe issue. In the nutshell, it looks like things are looking real good for a release sometime in 2012 (though perhaps we shouldn't expect anything before UPEW at the earliest).

About other chip configurations and/or process technologies, Chip said something to the effect of, while those are interesting/exciting possibilities, the team needs to focus on following through with the current design, which, of course, makes sense and is what we have all been clamoring for. Still, I really like Tony's above-mentioned 12-cog, 512KB 90nm "compromise" design (i.e., the process technology between 45nm and 180nm) because the additional memory would be so useful for certain designs without requiring going off chip for more. I can't help but wonder what it would take to make that happen, maybe just a commitment to the change (and reduced pressure from us). It sounds like significant portions of the current design (memory elements, etc.) could be replicated and it sounds like their synthesis partner is flexible and used to working with bleeding-edge designs.

Not to belabor this topic (please don't stone me), but, we've waited this long, so I, for one (perhaps the only one), could tolerate a few months of delay for a significantly enhanced version. I say this because, even though Parallax Semiconductor now exists as an entity, it doesn't sound easy for them to come out with multiple versions of chips, considering their current level of resources and the overhead costs associated with each chip design. Moreover, technology has advanced so much that a more powerful chip might be better received in the market place. On the other hand, based on what Chip said, producing other versions should be much more feasible now that they have attached the capabilities of the outside synthesis company. But I also heard Chip ever-so-slightly muse for a split second about a 64-bit architecture (who knows, maybe with more cog register address space or perhaps a third instruction register per instruction (src1, src2 and dest)), and perhaps something like that would more naturally justify the effort and cost to move to a 45nm process. Such a small process technology perhaps is a more natural candidate for a Prop III than a suped-up version of the current Prop II design (although bigger companies often produce such large chip families). As such, it might be the case that a somewhat more powerful/flexible Prop II chip (such as one meeting Tony's wish list) would fit better between such a possible Prop III and the current Prop. On the other hand, if Parallax has or can ramp-up the resources to do various versions, then sticking with the plan makes complete sense, and, arguably, sticking with the plan makes sense even if they can't marshal such resouces, too, because a Prop II of the current design represents a significant new device in and of itself.

Lastly, of interest was Chip's comment that his increasing confidence in his team's ability to work with the synthesis company has led him to consider changes and/or features that he would have never comtemplated using only the old methods (as implementing them would have been impossible in practice), and that he had needed to unlearn some of the formerly applicable rules and/or expand his thinking. That's pretty interesting to me because we sometimes wall ourselves in unnecessarily without even realizing it.

Bill Henning
10-29-2011, 03:47 AM
Marketing idea: Maybe they could use some of those fuses to disable 6 cogs and sell a cheaper, 2 cog version...

I HATE marketing gimmicks like that. Intel/AMD do this, and it is a sign of companies not really wanting to innovate, but wanting squeeze the last bit of blood from stone by spending more to make crippled parts to sell for less.

One cost-reduced design possibility would be 48 I/O's, 4 cogs, 64KB ram. It would be 1/2 the die size, and fit TQFP-64

SRLM
10-29-2011, 08:18 AM
Thank you for posting. Is there a target audience for the chip? It seems like in embedded systems world there is a strong divergence: high power systems (EDDIE, Linux based systems, etc) and very low performance systems (small AVRs, Arduino). The P2 seems to fit right in the middle.

frank freedman
10-29-2011, 10:33 AM
If someone were to start a pool on engineering sample availability, I would be picking christmas 2012. Just based on what chip had said plus a guestimate of complete testing / validation of all functionality. These test suites were what I was questioning regarding tools for P2.

Frank

Cluso99
10-29-2011, 11:34 AM
Whatever we finally get in the PropII it will be amazing. Meanwhile, the current Prop continues to reveal newfound treasures and thus uses never before considered.

Rayman
10-29-2011, 12:47 PM
I HATE marketing gimmicks like that. Intel/AMD do this, and it is a sign of companies not really wanting to innovate, but wanting squeeze the last bit of blood from stone by spending more to make crippled parts to sell for less.


I think it makes a lot of sense... The market is very tight these days and they just said how much $$ and time it takes to create a new design. But, if you can use the same design for two products, you really save.
Plus, the customers benefit from having a choice. If they would sell more chips and make more money doing this, isn't that a win, win?
Maybe another way to go it to limit the operating frequency on one version.
Or, you could have a package with less I/O pins and increased pin spacing (easier to solder by hand).

One the other hand, Parallax does seem to stand out by having just one version of a chip.

cgracey
10-29-2011, 05:28 PM
I'll restate some things from the Thursday webinar, for clarity.

We seem to be about eight weeks from completing the main synthesized logic block that forms the brains of the next Propeller chip. I don't know how long it will take from there to get the production chip out.

The mask cost for this 180nm process is about $150k. Currently, the design is synthesizing and laying out at 180MHz. That means 180 MIPS per cog, for a total of 1,440 MIPS per chip. I'm really pleased with how things are moving along. It's been a big learning experience. To put 180 32-bit MIPS into perspective for us old-timers, an Apple II would have taken (if I remember) eight instructions to add two 32-bit (4-byte) values together (existing in zero-page, for efficiency). Eight clocks at 1MHz would mean 125,000 32-bit adds per second. If you divide 180,000,000 by 125,000, you get 1,440. So, a single cog could be said to have 1,440 times the computational ability of an Apple II. And there are eight of those! And when it comes to multiplying, instead of 1,440x, the speed increase jumps to probably 60,000x.

For fun, I asked the company that is doing our synthesis work to pass our design through a 40nm-process design flow (TSMC 45G, which I mistakenly called '45nm' in the webinar). I was interested to hear how fast the design could run at 40nm. I was thinking it would top out at ~600MHz. It turns out that it closes timing at 1GHz! That's 1,000 MIPS per cog. Imagine 1,000 instructions every microsecond. If we were to build a version of the Propeller in this 40nm process, it would probably have 16 cogs and 2MB of hub RAM. Imagine 16,000 MIPS per chip! That's 100x the performance of the current Propeller chip. The only big roadblock to realizing this is the $3M required for the mask set.

Back to the current project... Below is a colored map of the currently-synthesizing 180nm logic block that includes the eight cogs and hub circuitry. Each color represents the circuitry of a particular cog. Nobody told the tools to make a pie. They just did that, since each cog's support memories are located in a circular pattern around the perimeter of the block, and each cog mainly connects to its own internal circuitry. Where they come together in the center, there is a lot of wiring congestion. At first, we tried to arrange the cogs as rectangular blocks arrayed left to right, with their memories overhead. It wouldn't route because of the many lateral wires required to connect them all together. This rotational layout is much better, because the cogs can converge in a common point and this reduces the heck out of the wiring required among them.

86436

The dark cyan splotches in the bottom two pie slices belong to the cogs they are within, but because some logic paths were optimized, they lost the label associations that tied them to the cogs they belonged to. In this mass of logic, there are 378k standard cells and over 200k nets. The actual cell area is 8.05 square mm. The layout area is about 14 square mm to afford some interstitial spaces for buffering and the clock tree. It would take person forever to do this, let alone the optimization and path reduction to get the whole thing to meet timing requirements. It took their computers only several hours to do this (along with a few $M of software).

Loopy Byteloose
10-29-2011, 06:05 PM
Thanks Chip, and thanks Ken. Product development of any kind takes real courage as it requires endless patience. This is all rather exciting and amazing to follow - and an honor that you let us in on the actual development. It is wonderful to know that one day soon, the Propeller II will be challenging us with new ideas and new horizons.

I am hoping that you will have something by Chinese New Years, but waiting is half the fun.

Rayman
10-29-2011, 06:09 PM
That's a cool image Chip. Why isn't it symmetric? You should put those computers back to work until they come up with 8-fold symmetry :)

Heater.
10-29-2011, 06:13 PM
Is it normal now a days to have such organic looking chip layouts? Over the years from time to time one gets to see chip floor plans and they have always been regimented rectangular areas. This is something else, at least from where I'm looking.

mindrobots
10-29-2011, 06:20 PM
Thanks for sharing! With speeds like that, I'll have REALLY fast poorly designed code!!!

1ghz.....hmmmm, if every prop customer chipped in $20 or $50 how much could we raise? Think of it as open sourced funding or user community funding. It could take a bite out of the R&D cost for Prop 3 and our return on investment would be having the chip. The rewards of investment funding don't always need to be some % growth on your money. A Prop 3 has certain "intangible" benefits to many of us including growth and success for Parallax which really benefits all of us.

Open up the "Kickstarter" project. I'm in at the $50 level!

rod1963
10-29-2011, 07:32 PM
It would take 60,000 Prop customers each paying $50 to get to the $3 million. Good luck with that.

Still I don't get where is the market for a stripped down PropII? Because you will be competing directly with the likes of the M4 ARM's from ST and Freescale along with the offerings from TI and Microchip for market share.

Martin Hodge
10-29-2011, 07:44 PM
You know, if Makerbot can get $10M in venture capital for their burned plywood printers, why can't Parallax get a measly $3M for a possible game-changing silicon IP? I guess it really does boil down to "who you know".

rod1963
10-29-2011, 08:04 PM
Martin

If Parallax scores a decent design win with the Prop II then they'll have the cash to do the 1Ghz version. It will be interesting to see the Prop II going head to head with some of the ARM designs out there like the Da Vinci(which I think Parallax is targeting with the PropII).

frank freedman
10-29-2011, 08:15 PM
You know, if Makerbot can get $10M in venture capital for their burned plywood printers, why can't Parallax get a measly $3M for a possible game-changing silicon IP? I guess it really does boil down to "who you know".
]
Actually has anyone ever met a venture capitalist or group that would not demand a certain amount of control and guaranteed performance milestones? HHmmmm, neither have I. Would Chip make lots of money? Probably. Would he loose control of the company? Sharper players than he have. Would it be as fun for him? Hell no. He has a great product now, designed at the his pace for his own good reasons. Are we happy? Yes, to paraphrase Jim Kinkaid "but like children everywhere, prepared to ask for more". Hence the drooling or whatever over the prop 2.

Not having the Prop 2 right now will not kill the company, I can do stuff with it I can not do as easily as say a PIC, but for dsp or compute intensive the Prop is not my choice. Pick the most suitable part. Seems lots of people like the suitability of the prop as is; and when the prop 2 comes out will do the same. Maybe less the hobbiests understand that, but those doing this for a living (should) have this outlook cold. Or they quickly become hobby level.

Just my $0.02USD worth. By the way, who will be starting the release date pool????

Frank

4x5n
10-29-2011, 08:24 PM
Personally I think it's time to get the prop II as is into production and out into the market place. From what I've seen of the other chips on the market the prop II will be revolutionary not evolutionary!! I'm looking forward to getting my hands onto a gadget gangster type board and seeing what I can do with it!

Leave the 40nm 1GHZ 16cog microcontroller with 2meg of hub ram for the prop III! At some point a product has to come to market!

Publison
10-29-2011, 09:12 PM
Thanks for the update Chip!

Unfortunately, I fell asleep for the last hour (Midnight to 1:00 AM here)

Will catch up when the Webinar is posted.

Jim

Martin Hodge
10-29-2011, 09:29 PM
Frank, it wasn't my intent to question P-Semi's decisions. Just make a comparison on what VC's are and aren't willing to fund.

potatohead
10-29-2011, 09:34 PM
You know the pie shape is striking!

Kind of makes sense though, given how the device operates. Those synthesis tools are very interesting Chip! Amazing software really. So many optimizations in such a small amount of time. Thanks for the color image. Intriguing...

I often see similar artifacts on mechanical CAD simulation, and or fluids. What we think is optimal, so often isn't. Simulation software can yield surprising results, and the most interesting part about it is once they are seen, the people then can make much better mental predictive decisions. Valuable stuff. Another area that always exhibits this quality is plastic mold injection simulation. What makes good common sense, often isn't! The flow dynamics of the plastic, and the thermal edge effects play out in ways often hard to just visualize without first running a simulation or two.

This is the first time I've seen it play out on chips, and am expressing the same intrigue Heater is! I'll bet you learn a lot on that simulation Chip! Thanks for sharing the process with us. Appreciated.

Did those guys have any comments, BTW? Would be really interesting to hear what they thought of how the simulation played out, or if they saw similar organic things appear on other devices?

Re: Capital and control.

Frank nailed it! I'll bet they could get the money, but then again, there would be some significant expectations attached to it, not all of which would align with how Chip and Parallax prefer to work. There are distinct advantages to keeping a company held private, and this is one of them.

Typically, a investment of that kind would require a percentage company ownership, IP management, and a person placed in a position of power at Parallax to manage the return on that investment.

frank freedman
10-29-2011, 09:50 PM
Frank, it wasn't my intent to question P-Semi's decisions. Just make a comparison on what VC's are and aren't willing to fund.

Did not take it as such. If I could dump some money in there I would, but not without strings. Many out there are not as familiar with how the game works as evidenced by various postings across the forum and time.

I could develop serious envy of Chip and the ability to play and get paid for it. I know reality is much more complex, but then again my job is serious play as well and I enjoy what I do too. So my play time is a bit restricted.....

Work to play, and play to work...

Frank

4x5n
10-29-2011, 10:45 PM
Martin,

My comments weren't directed at anyone in particular. I was just pointing that it's important to release the prop II as is and after it's in production start work on the prop III!

Cluso99
10-29-2011, 11:35 PM
Thanks Chip :)

Questions on the current design (if you have time to answer)
1. Does the current design actually have a full 128KB of hub sram but ~2KB of that is inaccessable because of ~2KB of ROM? If so, could not the ROM be mapped out after boot to give this up to the sram, or alternately sit in top of hub (i.e. A0-16=128KB, so A17=0 for ram and A17=1 for ROM or visaversa, so ROM will just repeat every ~2KB. Hate to waste 2KB ram for a few gates.


Current floor plan
I guess the rectangular approach we expect are from our human approach to put things into a block so we can duplicate that block. But once you get to a certain complexity it takes forever. Conceptually, they are the same sort of issues from a PCB design point of view. Without human constraints, very expensive and intelligent software can do these things very fast. Perhaps not to the same level that a human can, but with the complexities nowadays the human would take many man years. So reality steps in. The pie shape is not all that unusal in retrospect.

40nm version PIII (dreaming)
If I were to do a 40nm version, I would be opting for some master cogs. Think of these cogs as an ultra-fast processing cogs. Let the normal cogs do the I/O work. Give the master cogs just basic timers, no access to I/O pins, 2x hub accesses, and with the space saved put more of them. With this concept it could be possible to have 8 of these cogs instead of the extra 4 standard cogs. BTW 2MB of hub ram would be a dream (less ~2K ROM)

Venture Capital
We went down this line in the mid 90's. It is easy in the USA but we would have to move there from Oz. They want control of the company although they do provide the excellent support to permit the designers to just get on with the design without having to run the company too. In Parallax's case, they already have a nice company which is able to fund, albeit not as much as venture capital, their new designs. Chip & co control the company in the way they like. Really, why would you want to do this and give up control. It would become more of a chore than a hobby (because all Parallax staff seem to treat their work as enjoyable).

Forum Funding for Prop II
Lets look at this realistically. If 100 forumistas put in $100 that is only $10K. Even if we found 1,000 it is still only $100K. What might we want for that... maybe a prototype chip (not the shuttle because they are very low volume and expensive??) and a first run chip. Now, would that help Parallax... not likely. The issues are man hours and we cannot buy another Chip Gracey. At this late stage any extra help in addition to Beau would most likely slow down, not speed up the design process at this late stage. So, unfortunately, unless some were willing to throw serious money to move to a smaller die geometry such as 90nm (whatever the technical term is) then the whole question is really moot. Nice suggestion but not practical. And lastly, perhaps the work in pad design around the chip edges, and the hub ram and cog ram may have to be redone for a smaller geometry???

Reduced cost disabled chips
This question always starts arguments. It was used extensively in the mini and mainframe computer business very successfully. It enabled a company to sell cheaper computers (with less profit) to boost sales while not taking away from them the core business, giving them more economies of scale. maintenance was also more efficient as engineers needed to carry less spares.
The main reason companies do not disclose this fact is because of user anger as they do not understand the internal business models.
In chips, sometimes it is a yield problem. The company can now sell an otherwise useless part. Or it may be a speed issue. The cost of testing for the higher spec would weed out the better chips which could be sold for a premium. Once the required higher speed yield was reached, the remainder would not be tested for the higher speed. The result was pot luck on the lower speed devices as to whether they could go at a higher speed. Do not knock the concept. If Parallax sees an opportunity to boost volume for lower return on the extras, they will decide with their business model. This is business realities guys.

Heater.
10-29-2011, 11:59 PM
Blimey, haven't got the Prop II out the door yet and there is all this Prop III speculation arising.

Prop III will of course be 64 bit. That then allows for up to 32MB of COG space. There would be no need for on chip HUB RAM but rather use some serious COG to COG links. Which would also transparently link to COGs on othe chips for potentially huge arrays of processors. All running at 2 to 4 GHz naturally.

There, can that put an end to it?

4x5n
10-30-2011, 12:12 AM
Blimey, haven't got the Prop II out the door yet and there is all this Prop III speculation arising.

Prop III will of course be 64 bit. That then allows for up to 32MB of COG space. There would be no need for on chip HUB RAM but rather use some serious COG to COG links. Which would also transparently link to COGs on othe chips for potentially huge arrays of processors. All running at 2 to 4 GHz naturally.

There, can that put an end to it?

With the lead times for new products it's not unusual for a company to start work on the replacement for a product that hasn't even made to market yet.

Rayman
10-30-2011, 12:18 AM
Anybody know, can PropII die fit into Prop1 QFP package to make a drop-in replacement?

Heater.
10-30-2011, 12:22 AM
That is true. If you are an Intel or such you probably have multiple teams working on multiple generations at the same time, pipeline fashion. Not to mention teams working on ventures that never pan out, like Intel's 432 or 960 or Itaniums.

But this is Paralax with one small team to work on one thing at a time. Besides where is the fun in it for Chip to have a team designing the thing for him?

4x5n
10-30-2011, 12:39 AM
That is true. If you are an Intel or such you probably have multiple teams working on multiple generations at the same time, pipeline fashion. Not to mention teams working on ventures that never pan out, like Intel's 432 or 960 or Itaniums.

But this is Paralax with one small team to work on one thing at a time. Besides where is the fun in it for Chip to have a team designing the thing for him?

From what I can tell Parallax is to small of a company to have multiple design teams working on future generations. In the case of the prop II it's been a long time in the making and if Chip/Parallax continues to redesign the prop II with every change in technology there will never be a prop II. It sounds like the design of the prop II is pretty much set (I missed the webinar earlier this week) and about ready to go into production. Rather then continue to add more features and go with 40nm technology, etc, etc I say they should release what they have as the prop II and look into the 40nm technology, 16 cogs running at 1GHZ, megabytes of hub ram, etc for the prop III!!

Heater.
10-30-2011, 01:27 AM
16 COGs is not a good idea. It halves the bandwidth into HUB memory effectively stealing half your clock speed. As you have more memory then it would be better to have more bandwidth to get at it with.
Hence my dream Prop III with wider COG registers 40 to 64 bit, allowing huge COG space. No HUB hence no bandwidth issues competing with other cogs for access. High speed COG to COG interconnect instead.

zoopydogsit
10-30-2011, 01:33 AM
I like the update and the opportunities that have been canvased.
If I had a couple of $M available I'd seriously consider investing in the opportunity. I can see immense potential.

My thoughts on the discussion;
- Finish the Prop II as is, before deciding on the next path. I agree that there are wonderful possibilities with the 40nm technology, hub ram being one of them! However there are still learnings to be gathered from the current plan that should be completed before deviation. Please don't get distracted by something shiney, I see too many technical people never completing what they do because of these temptations.

- Funding. I don't know the regulatory and overhead costs of a private company seeking to raise funding, I've heard listing fees at stock exchanges are prohibitive. However, if they sought to raise capital today, I'd be excited to invest in Parralax Semiconductor to raise money for the 40nm technology. Though this would be a serious financial investment into Parallax Semiconductor (and it's intellectual property), not be a gift, nor would it be to buy a proto copy of the chip. If they were not able to be traded (ie. could not have a way to resell them) then I'd expect a regular dividend from the investment should the profitability of the company increase from the investment (some kind of agreed legal binding formular based on performance would be needed in the proposal). In regards to control of Parallax, I'd be fine for these to be "non-voting" shares leaving the running of the company to the Graceys - fine job they've been doing over the last 20+ years. Maybe they could consider a Parallax Semiconductor IPO? Under my current financial circumstances I'd probably invest about $1K in such an enterprise (maybe more based on the proposition), though it would be dependent on my financial circumstances at the time (as we've seen, situations can change rapidly). I could see this funding other things like the Prop I-B (there is still a lot of puff in the current work-horse, it's just short of pins to capitalize on it's capabilities, and it just runs on 3.3V). To protect my investment, one thing I would require in the IPO is that Parallax Semiconductor develop a code security strategy, as this may be a problem for sales in the future.

frank freedman
10-30-2011, 04:25 AM
Funding and the rest: ya put the finish, clearcoat and polish on my points by example!!

Frank

jmg
10-30-2011, 04:58 AM
One cost-reduced design possibility would be 48 I/O's, 4 cogs, 64KB ram. It would be 1/2 the die size, and fit TQFP-64

Such cost-down variants usually come along later.

A better trade-off in my opinion would be a variant with less COGS, allowing more precious RAM, and with a Multi-thread option on the COGS.
(that would allow a 180MHz.512W COG, to also act as two 90MHz 256W COGs (or even 384/128 COGs etc )
This softens a drawback in Prop, which is the inability to share resource and lack of 'soft edges' in limits.

Cluso99
10-30-2011, 06:22 AM
As I understand the Prop II design today, the outer perimeter of the chip is cast in stone. That is all the I/O routing and all the I/O pin design. Also, I understand the blocks of hub ram are done (although adding/removing blocks is possible) as are the cog ram blocks (although rearranging the rectangular/square attributes can be modified).

That just leaves the cogs including the instruction set and counters and the interfacing to the hub and interfacing to the I/Os. This has been done in Verilog and has been the source of the recent delays due to critical paths and the computer routing. it seems this is now well advanced.

I would presume there are no real hardware changes contemplated.

The 40nm discussion was just a nice sidetrack question raised by Chip to the layout people. We can speculate all we want (as I have done) but in reality, its not going to happen. I would even think that if I were to put $3M on the table (I dont have it!) with no strings attached, it would make no difference.

I am just in awe of what can be done with smaller geometry, and not really significant cash.

Mickster
10-30-2011, 10:33 AM
Such cost-down variants usually come along later.

A better trade-off in my opinion would be a variant with less COGS, allowing more precious RAM, and with a Multi-thread option on the COGS.
(that would allow a 180MHz.512W COG, to also act as two 90MHz 256W COGs (or even 384/128 COGs etc )
This softens a drawback in Prop, which is the inability to share resource and lack of 'soft edges' in limits.

Cogs already have the capability of multi-threading by using JMPRET :smile:

Mickster

Heater.
10-30-2011, 11:19 AM
Depends what you mean by multi-threading.
Coopertive threading can be done in many ways and JMPRET is a quick and convenient way on the prop. However it does rely on the programmer sprinkling his code with JMPRETs appropriately. It also means not using WAITxxx which would hang all threads. And that means external events may not get handled as quickly or predictably as you would like.

Preemptive scheduling can also be done in many ways. One simple technique is to execute a single instruction from each thread in a round robin fashion. Each of N threads gets 1/N of the available MIPS, has know fixed latency to events and can use WAITxxx. Also performance is higher as no extra JMPRET instructions are needed which in the worst case eats half your MIPs.

All in all such hardware threading is a neat, simple solution. Rather like the round robin HUB access idea.

__red__
10-31-2011, 12:53 PM
Speaking of information regarding the PropII, I thought I heard Chip mention that we were clear to post the PropII Assembly Instructions...

Was that the case? Can someone do it please :-)

Thanks,



Red

jazzed
10-31-2011, 03:09 PM
We are working on it ....


Speaking of information regarding the PropII, I thought I heard Chip mention that we were clear to post the PropII Assembly Instructions...

Was that the case? Can someone do it please :-)

Thanks,



Red

Circuitsoft
11-01-2011, 03:50 AM
For fun, I asked the company that is doing our synthesis work to pass our design through a 40nm-process design flow (TSMC 45G, which I mistakenly called '45nm' in the webinar). I was interested to hear how fast the design could run at 40nm. I was thinking it would top out at ~600MHz. It turns out that it closes timing at 1GHz! That's 1,000 MIPS per cog. Imagine 1,000 instructions every microsecond. If we were to build a version of the Propeller in this 40nm process, it would probably have 16 cogs and 2MB of hub RAM. Imagine 16,000 MIPS per chip! That's 100x the performance of the current Propeller chip. The only big roadblock to realizing this is the $3M required for the mask set.
What no one else seems to have asked yet, is, how many Prop-2s would you need to sell to make up for the Prop2 R&D and produce this? (Prop2-A vs Prop2-U; See AVR32-A vs AVR32-U for source of naming convention)

rod1963
11-01-2011, 06:34 AM
You have to wait until the PropII can chalk up enough volume design wins to warrant this move. That's the key.

jmg
11-01-2011, 07:55 AM
Preemptive scheduling can also be done in many ways. One simple technique is to execute a single instruction from each thread in a round robin fashion. Each of N threads gets 1/N of the available MIPS, has know fixed latency to events and can use WAITxxx. Also performance is higher as no extra JMPRET instructions are needed which in the worst case eats half your MIPs.

All in all such hardware threading is a neat, simple solution. Rather like the round robin HUB access idea.

Yes, that is pretty much what I had in mind. Simple time-slot stuff, likely limited to a single word load to configure.
16 bits would allow 8 time slots to 'any of 4' threads, 24 bits would allow 8 time slots to 'any of 8' threads + 8 semaphores => 1 word.
'Any of 8' would allow up to 1/8 : 7/8 skews on two tasks, or 8 identical 1/8 MaxMIP threads (etc)
Total code limit does not change.

FredBlais
11-02-2011, 01:01 AM
You know, if Makerbot can get $10M in venture capital for their burned plywood printers, why can't Parallax get a measly $3M for a possible game-changing silicon IP? I guess it really does boil down to "who you know".

Why not post the 1 GHz Propeller II on http://www.kickstarter.com/ ? hahaha =D

RinksCustoms
11-02-2011, 04:00 AM
i heard rumor about the recent webinar being posted for all us late bloomers.. . where might that be? the webinars posted @ parallaxes website are stale like moldy bread (like 2009 last posted)

Ken Gracey
11-02-2011, 04:35 AM
i heard rumor about the recent webinar being posted for all us late bloomers.. . where might that be? the webinars posted @ parallaxes website are stale like moldy bread (like 2009 last posted)

That makes two of us who are looking for the webinar, so I'll find out where it is. I had to leave when Andy was talking about the PropBOE so I want to watch it now, along with Chip's presentation.

Ken Gracey

Lauren Davis
11-02-2011, 07:11 AM
The recorded meetup webinars can be found here http://forums.parallax.com/showthread.php?128723-Propeller-Meetup-Group-Invite. We also added a link from the http://www.Parallax.com/go/webinar page to the archives so it's easier to find. Let me know if you have any difficulty.

Kevin Cook
11-02-2011, 03:43 PM
Better yet, here is the forum sticky for the Meetup Group which has the webinar recordings.

http://forums.parallax.com/showthread.php?128723-Propeller-Meetup-Group-Invite

RossH
11-02-2011, 11:12 PM
Speaking of information regarding the PropII, I thought I heard Chip mention that we were clear to post the PropII Assembly Instructions...

Was that the case? Can someone do it please :-)

Thanks,

Red

Hi Red,

I wouldn't hold your breath. I haven't caught up with the full webinar discussions yet, so I'm not sure what Chip actually committed to - but I seem to remember he promised the Prop II instruction set after the previous webinar as well (maybe six or nine months ago?) and it never eventuated then either. Yes, I know he has lots to do, and we would all rather he got on and just finished the Prop II ... but still ... :frown:

Ross.

jazzed
11-02-2011, 11:27 PM
I wouldn't hold your breath. I haven't caught up with the full webinar discussions yet, so I'm not sure what Chip actually committed to ...
I bugged Ken about this yesterday. I'm looking for it to show up any time now.

Ken Gracey
11-02-2011, 11:31 PM
Yes, within the day it should be posted. - Ken

RossH
11-02-2011, 11:59 PM
Yes, within the day it should be posted. - Ken

Thanks Ken - I look forward to it!

Ross.

Ken Gracey
11-03-2011, 12:16 AM
And we should thank jazzed for helping us understand the importance of making the Propeller 2 instruction set available. He's been an important link to the forums for us lately, with PropGCC being a very key example. Thanks Steve!

Ken Gracey

Daniel Harris
11-03-2011, 02:03 AM
Good evening gentleman and ladies,

Without further ado, the Propeller II Preliminary Feature List (which contains the Propeller II's instruction set).

Enjoy!!! :D

========================================

http://www.parallaxsemiconductor.com/Products/propeller2specs

========================================

RossH
11-03-2011, 02:47 AM
Good evening gentleman and ladies,

Without further adieu, the Propeller II Preliminary Feature List (which contains the Propeller II's instruction set).



Great! Thanks, Daniel. A few people had been wondering what happened to the "open and inclusive" Parallax we all used to know and love. But now all is good again :)

Ross.

Rayman
11-03-2011, 03:06 AM
Well, the first think I looked for was the multiply instructions (because I've been waiting a long time to do MP3 decoding...).
Took me a minute to figure it out, but I see a 16-bit multiply, so I'm happy!

I think they can leave off the "(0-511)" everywhere for D and S though. Isn't this understood?

I really don't see how "waitpeq" can be the same as Prop1...

I like the external ram instruction!

Don't see the point of chip-chip comms...

ratronic
11-03-2011, 03:28 AM
Just finished reading the preliminary feature list and Chip has been a busy man!

Tubular
11-03-2011, 03:57 AM
Wow, what a beast...

Beau Schwabe
11-03-2011, 04:02 AM
RossH,

"...A few people had been wondering what happened to the "open and inclusive" Parallax we all used to know and love. But now all is good again..." - We've been sort of busy. :-)

SRLM
11-03-2011, 04:35 AM
The System Counter counts the number of clock ticks since power up – it is a 64-bit counter,

So, the counter should be able to run for 1.3 million days at 160MHz before rollover...


The IND registers allow indirect register access to avoid self-modifying code.

Isn't self modifying code one of the good unique features of the Propeller?


Cogs now have the ability to remap their internal memory to help facilitate context switching between register banks. Instead of having to save a bunch of internal register to switch running programs all references to a set of register can be changed instantaneously.

Fun! It sounds like a tactic I learned in my OS class...

It's interesting how the terminology has changed from the Propeller 1. It seems that the Parallax employees have been reading up on datapath creation, and started using new (for the Propeller) terms such as "register", "FSM", etc.

pjv
11-03-2011, 04:52 AM
@Parallax;

Thanks !!

Quite a beast indeed! It will take quite a while to get my head wrapped around this one..... in fact at first blush it all looks a bit daunting, but I suspect that with time it will become manageable.

Sure will be fun to mess with though.

Cheers,

Peter (pjv)

Cluso99
11-03-2011, 05:05 AM
Has anyone else had problems opening the file? Acrobat reports an error in the file and refuses to open it. I have tried updating Acrobat, but it still reports an error.

RossH
11-03-2011, 05:17 AM
Has anyone else had problems opening the file? Acrobat reports an error in the file and refuses to open it. I have tried updating Acrobat, but it still reports an error.

Yes, there does seem to be an issue. I can open it, but it has crashed my Adobe reader once already. One trick with pdf readers (especially Adobe) is never to open a pdf in a browser - always download them and open them locally.

Ross.

Cluso99
11-03-2011, 05:21 AM
No. Both Adobe Reader v9 and v10 refuse to open it :(

RossH
11-03-2011, 05:24 AM
I have Adobe 10.1.1. It crashed the pdf reader the first time I opened it in the browser, but loading it locally seems ok.

Ross.

Kal_Zakkath
11-03-2011, 05:34 AM
Just some free proof-reading for those at Parallax: :)



Page 1 - Introduction

Each cog has 512 longs (2 KB) of memory from which it executes instructions from.






Page 11 - Table 1

When written changes the state of the I/O pin attached to port B. When read, returns the state of the I/O
port attached to PINC.
When written changes the state of the I/O pin attached to port B. When read, returns the state of the I/O
port attached to PIND.



That's for PINC & PIND.

Also:


Page 12 - Table 15

Assign PORTC to physical I/O ports (0-2) or
internal I/O port 3 given register “D (0-511)” or
number “n (0-3)”.



on SETPORD (our old friend copy & paste strikes again!)


Lastly:


Page 13 - Table 18

Sets up the serial port I/O pins to use for SO, SI,
and CLK given D or “n (0-63)


Not sure if this is a typo or not - chip-to-chip comms may not be available on port C?

Bob Lawrence (VE1RLL)
11-03-2011, 06:34 AM
re: No. Both Adobe Reader v9 and v10 refuse to open it

I used Adobe 10.1.1 in Google Chrome 14.0.835.202 for MS Windows 7. No problems so far.

Amazing Specs for Prop 2. :)

SRLM
11-03-2011, 07:28 AM
I can open it using the Evince document viewer on Ubuntu... I printed to PDF, so perhaps this version will work right:

86557

ps: and really, I didn't change a bit here and a bit there. I take out a whole byte when I munch...

Ale
11-03-2011, 07:41 AM
Amazing stuff... There is also a 32x32 MUL !. No problems with Snow Leopard's preview for the pdf.

Cluso99
11-03-2011, 07:43 AM
I have IE8 but I did save the file and tried to open outside IE too. All failed.

SRLM: Success - thankyou :)

Cluso99
11-03-2011, 09:24 AM
Nice instruction set with a lot of great features. Just a couple of things I noticed...

The instruction to toggle a pin on or off...
The mnemonic OFFP seemed obscure/incorrect. I wonder if NOTP, XORP or TOGP may be more intuitive ???

There did not seem to be any hardware assist for receiving bitstreams within the counters. Did I miss something, has it just not made the specs, or is it not going to be possible ???

A few instructions will require better explanations later because I could not determine what they actually do, and their use.

There are a few really powerful instructions that will minimise code. For example the NOPX instruction will be great for timing data streams etc. The REP instruction (we knew about this) will be fantastic. The hub instructions with incrementing and caching options will remove a bottleneck, as will quad and 1in8 rather than 1in16 clock accesses too. And the ability to use the CLUT when Video is not used will also be a great addition.

All-in-all, it will be the great chip we are expecting :)

Sapieha
11-03-2011, 10:31 AM
Hi Daniel.

Thanks for posting this List of instructions.

Some of them still need some extra explanation but in first stage it is OK.

I have one more question to You/Chip -- as it is not clear from this List to find answer!

How many pins VGA will use ? 4-5 else more(and need them some predefined pin places else any of pins) . Next what type of Boot device is planed to be used and how many pins need be reserved for that?




Good evening gentleman and ladies,

Without further adieu, the Propeller II Preliminary Feature List (which contains the Propeller II's instruction set).

This document will be posted here for the evening. Tomorrow morning, the document will be posted on the Parallax Semiconductor website and a link to the appropriate page will replace the link to the file.

Enjoy!!! :D

========================================

http://www.parallaxsemiconductor.com/Products/propeller2specs

========================================

Rayman
11-03-2011, 11:33 AM
If you still can't open the file, I've made it into a web page here:

http://www.rayslogic.com/Propeller/Prop2/Propeller2DetailedPreliminaryFeatureList-v1.2.html

jmg
11-03-2011, 11:51 AM
Good information.
a) I think I can see a 32*32 -> 64, but the divide is a little unclear, is that
a complementary 64/32 -> 32Q.32R
or a simpler 32/32 -> 32Q.32R
Q.R is great, as that allows fast modulus moths.

b) The Counter has Quadrature mode, which is great.
- but I can see no mention of any HW CAPTURE, and even external Divide from a Pin, is not clear ?

Why does this matter ? : You can get much better precision, and dynamic range, and lower power, if software tight polling is not needed.

With two 32 bit counters with capture ability, and atomic On.off control of the pair of flags (in same SFR)
and one counter clocked from High speed timebase and the other from any pin, you can build a very high precision,
and wide dynamic range counter.
One gives time, the other Cycles, and then Cycles/Time is Frequency. \
Precision is very high : At 180MHz and an (appx) 100ms refresh time, you resolve to 55ppb, 10ms refresh resolves to 0.55ppm, and 1ms refresh resolves to 5.5ppm. (1s resolves to 5.5ppb, and 10s can give 0.55ppb)

Sounds like this would have a very low added silicon cost ?

Tor
11-03-2011, 12:07 PM
The document opens fine in the readers I have. I don't have Acroread though.


[about the IND registers] Isn't self modifying code one of the good unique features of the Propeller?

I wouldn't call it "good".. to me it's a necessary hack due to missing indirection handling via registers and this improvement is one I wished for in Propeller II, so I'm happy. :-)

- I like the 'Cog Memory Remapping' although I'm curious about where it maps to and from.. it doesn't say more about it, from a quick look at the document.

- The Cog-To-Cog and Chip-To-Chip communication features look useful.

The biggest constraining problem with the Propeller compared to other architectures is of course memory.. it looks constrained even when compared to old 8-bit micros. Propeller II has more hub memory, but it's still very limited to someone used to be able to just address the memory you need, and then only look to VM methods for truly large stuff. So Propeller II is better, but still constrained - it goes with the architecture I guess. The streaming external RAM handling will probably be essential in a lot of projects..

-Tor

Ale
11-03-2011, 12:48 PM
Tor, the constrain is for code, as for data you have access to full 128K :). Not bad. As you probably have some cogs dedicated to do some kind of IO, they (at least some), as it has been proved time and again fit in 2kBytes. Large programs, well they are something that Spin partially takes care of. If you divide and conquer, this "limitation" goes partially away. Of course fully shared HUB memory from where opcodes are also fetched is the realm of some other multi-core processors (for instance cortex A9). Those need more power, resources and do not come in DIP packages (talking about Prop I here).

Bill Henning
11-03-2011, 02:48 PM
Thanks for posting this update!

I love the chip-2-chip communication, but it should also support sending/receiving 8 and 16 bit values - which would allow it to be used for very easy, super-fast SPI to/from peripherals!

ctwardell
11-03-2011, 03:05 PM
Wow...

Does anyone have any detail on the "Cog Memory Remapping"?

C.W.

Sariel
11-03-2011, 03:06 PM
Cogs talking to each other? Excellent news. I have a very limited understanding of Assembly (still working on learning it), and from what I can see, indeed. "Beastly" is the only word that comes to mind when reading up on this.

My hat is off to Beau and Chip. Very impressive work guys.

Ale
11-03-2011, 03:26 PM
btw, it is "without further ado" ;-)

jmg
11-03-2011, 09:31 PM
Thanks for posting this update!

I love the chip-2-chip communication, but it should also support sending/receiving 8 and 16 bit values - which would allow it to be used for very easy, super-fast SPI to/from peripherals!

Yes, looks great - but you are right, it certainly needs a Length control (and also the usual CLKSPEED and Polarity controls.
Less clear is if this has annoying 'gaps' between sends (no mention of a fifo) ?
I've also often thought SPI ports with good baud rate register control, should have a simple flag for continual CLKOUT use.

Kye
11-03-2011, 11:17 PM
Hey guys, please note the preliminary spec is vague about all the on board hardware devices on purpose. The documents goal is just to detail major features. As the P2 nears completion a more detailed image will appear. Until then enjoy thinking about the new features.

Each processor has 4 9-bit DACs. So, VGA potentially needs 5 pins.

The divide is is 32/32 -> 32R and 32Q.

The plan for the counter modules is to have them implement the Goertzel algorithm http://www.eetimes.com/design/embedded/4024443/The-Goertzel-Algorithm in hardware. That's what the SIN/COS stuff is for.

Unfortunately, there may not be hardware for incoming serial streams. It depends on what can make it into the design.

Please consider the new speed of the chip when thinking about device I/O.

Thanks,

BigFoot
11-04-2011, 01:56 AM
I listened to Chip's presentation but didn't hear anything about the SD-Ram interface, do any of you know how this
is going to work ?

jmg
11-04-2011, 02:21 AM
The plan for the counter modules is to have them implement the Goertzel algorithm http://www.eetimes.com/design/embedded/4024443/The-Goertzel-Algorithm in hardware. That's what the SIN/COS stuff is for.

That sounds like a lot of silicon ?
I hope the simple, more widely used stuff like HW Capture on the counters is not overlooked ?

Tubular
11-04-2011, 02:43 AM
The plan for the counter modules is to have them implement the Goertzel algorithm http://www.eetimes.com/design/embedded/4024443/The-Goertzel-Algorithm in hardware. That's what the SIN/COS stuff is for.



Kye with reference to that article, can you please elaborate on whether you are aiming to implement the "basic" (includes phase information) or "optimised" (no phase information) variant?

thanks
tubular

Cluso99
11-04-2011, 03:01 AM
With VGA now likely to only require 5 pins (down from 8), TV is possibly 1 (down from 3), this is going to release some pins.

I do sure hope the counters do provide a primitive method of reading serial streams. Even if just a couple of gates are provided to permit the existing logic to reverse the direction like the following diagram portrays...

86569

jmg
11-04-2011, 03:12 AM
I do sure hope the counters do provide a primitive method of reading serial streams. Even if just a couple of gates are provided to permit the existing logic to reverse the direction like the following diagram portrays...



Did you see this in the pdf ?
["Each cog now also features high-speed serial transfer and receive hardware for chip-to-chip communication. The hardware requires three I/O pins (SO, SI, CLK)."]

This SPI mode has 3 supporting opcodes.

Or do you want the counters to also be Serially Configurable - that adds a multiplexer to every flipflop, and will slow it down.

Depends how much 180MHz margin there is, as I'd not want the counters slower than the SYSCLK

Kye
11-04-2011, 04:12 AM
@BigFoot - The new chip will feature the ability to read/write 16-bit or 32-bit data from any bank of the 96 I/O pins and transfer that data to the CLUT for video output or to main memory. This is simply a hardware assist for each cog that reads data (possibly every clock) into the chip or writes data (possibly every clock) out from the chip. The cog will still need to manage the data stream but at a higher address directing level instead of having to read or write the data manually.

@jmg - The serial input and output commands are for cog to cog comminucation. Unless they have been updated since this information was produced... they are not general purpose. As from my above post. Each cog is now so fast that sending data serially by bit banging should not be a problem. I understand the desire for dedicated serial input and output hardware. However, Chip choose not to persue that in the new design.

@Cluso99 - The counters will feature more functional modes, however, I do not know what they are.

@Tubular - Each I/O pin features a high speed (like over 160Mhz) sigma delta ADC built in to it locally which can generate a serial bit stream that is transfered to a cog's counter modules. This serial bit stream is then acculumated to respresent the voltage on the I/O pin digitally. The accumulation is then compared to a preset frequency and phase accumulation to get the power and phase of the frequency choosen on that I/O pin. I do not know exactly how this works but the goal is to have the SIN and COS accumulator registers store the power and phase of the Goertzel Transform in them. Simply... this allows you to pick a compare frequency and a compare phase for a I/O pin and see what the power and phase of that frequency of the signal on the I/O pin is. By doing a frequency sweep on the counter the frequency domain of a signal on any I/O pin can be gotten.

jmg
11-04-2011, 06:04 AM
@jmg - The serial input and output commands are for cog to cog comminucation. Unless they have been updated since this information was produced... they are not general purpose. As from my above post. Each cog is now so fast that sending data serially by bit banging should not be a problem. I understand the desire for dedicated serial input and output hardware. However, Chip choose not to persue that in the new design.


Are you sure ?
The heading says
["Chip-To-Chip Communication"]
and more text says
["Sets up the serial port I/O pins to use for SO, SI, and CLK given D or “n (0-63)”."]

That sounds to me like it is chip to chip via physical pins ? If not, they need to rewrite that part of the data.

Cog to Cog has a different heading:

Cog-To-Cog Communication
Cogs now have the ability to communicate directly to each other using the internal I/O Port D, which connects each cog to every other cog.
Table 20: Cog-To-Cog Communication Instruction Machine Code Mnemonic Operand Operation
000011_zcn_1_cccc_nnnnnnnnn_011101000
SETXCH D/#n Reconfigure Port D I/O masks given D or n to select which cogs to listen to.

but this is vague on what happens next. Is this talking about virtual (buried) pins ?

Cluso99
11-04-2011, 12:25 PM
jmg: This is for comms between prop chips and uses 3 pins.

What seems to be missing, and I did think it was going to be included, is some method to receive in a serial stream of bits. It does not have to be asynchronous etc, just the ability to shift in serially into a register (and the 32 bit register makes the most sense and would be the easiest). As can be seen, just a couple of gates per counter makes serial input easy. The counter could be configured with all the modes possible to clock it. Without this, we will not be able to do such things as USB without multiple cogs. This would be a real shame - just my opinion.

The D port is a buried 32bit port designed for fast comms between cogs.

jmg
11-04-2011, 12:46 PM
jmg: This is for comms between prop chips and uses 3 pins.

What seems to be missing, and I did think it was going to be included, is some method to receive in a serial stream of bits. It does not have to be asynchronous etc, just the ability to shift in serially into a register.

I'm not sure I follow, The SPI shifter looks like it can Send and receive, what is missing ?
Do you need an external CLK signal (SPI Slave ?) - but if it does Chip-Chip, one must be a slave so that will be in there ?

(no detail on gaps, etc ) If there are spare opcode bits, they could set the Length (1..32) ?



The D port is a buried 32bit port designed for fast comms between cogs.
So is this like a peephole cross point R/W (no contention) where any pair (or more?) can communicate with no side effects ?
Or do all Cogs have to 'take turns' ?

Sariel
11-04-2011, 01:18 PM
So is this like a peephole cross point R/W (no contention) where any pair (or more?) can communicate with no side effects ?
Or do all Cogs have to 'take turns' ?

I am under the impression that "Port D" is in addition to the hub interaction, so I don't think they would have to take turns... but someone please correct me if I am wrong.

photomankc
11-04-2011, 02:08 PM
Hope this is not a stupid question but I couldn't tell from the PDF.... does anyone know if SPIN will be able to handle floating point or is it still going to require using a cog+library functions to handle a floating point value?

Heater.
11-04-2011, 02:45 PM
I suspect that port D works like any other Prop port.
Every cog gets it's own input/output/direction register for it.
Any cog can access it at any time, as they do for the Prop I port register.
Writes will be OR'ed together to get the final "output" on the pin that any cog can see with IN.
Only difference being there is no actual hardware pins coming from it.

Could be wrong but that seemed to be how the discussion was going about it a while back.

Kye
11-04-2011, 06:34 PM
@jmg - Sorry, what I meant was that the serial communication commands send out 32 bit words through a fixed piece of RTL state machine logic. It isn't flexible so it will not be useful to much more than using it to talk between chips.

Port D is an internal set of 32 I/O pins. They can be read and written as if they were regular I/O pins. They just have no external connection.

@sariel - No floating point. This is common, however, for most microcontrollers. FP will be far easier with the new instruction set and hardware devices.

Also, the P2 will contain the ability to remap port A,B,C,D with each other. This allows you to write a program which always uses port A but with one command can move the bank of physical pins it talks to between 0-127. Only 0-95 are external, however. This must be aligned. So you can only remap to 0, 32, 64, 96 in the pin address space.

photomankc
11-04-2011, 07:31 PM
Oh well, hardware multiply and divide are nice all on thier own and i imagine they greatly simplify doing the FP in code. I just don't like haveing to burn a cog up to multiply or divide by 1.5 when needed but given the hurt I've been going through getting another micro to juggle several tasks at once It's a small price to pay. This looks like an awesome chip for a later upgrade to the robot brains I'm working on.

Kye
11-04-2011, 08:28 PM
With full C support and space to fit a FP library you will not need another cog. =)

Go GCC!

Also SPIN will be more than 8X faster so a software implementation will be possible.

photomankc
11-04-2011, 08:37 PM
Sweet. I'm much looking forward to GCC as well! Very excited about the speed boost for spin. That puts lots more stuff in reach.

jmg
11-04-2011, 08:54 PM
@jmg - Sorry, what I meant was that the serial communication commands send out 32 bit words through a fixed piece of RTL state machine logic. It isn't flexible so it will not be useful to much more than using it to talk between chips.


SPI is plenty smart enough for many tasks, and if there are 'no gaps' you can make useful PWM DACs out of it....
However, it really does need length control ability.



Port D is an internal set of 32 I/O pins. They can be read and written as if they were regular I/O pins. They just have no external connection.

Thanks, so it is as I originally thought - what I called virtual (buried) pins.

IanM
11-06-2011, 01:46 AM
Can the phase accumulators be configured to run through the SIN or COS registers and then through the D/A converter to create a DDS running at the clock frequency? That would be awesome!

Ian

Kye
11-06-2011, 03:50 AM
You can output clean sine waves and such. So... yeah, the counters can run higher than the clock frequency.

hinv
11-06-2011, 05:10 AM
What is the status of the last 4 pins of port C? Are they available like port D buried pins?

Ale
11-06-2011, 09:23 AM
I think hinv question is a very good one. Each propeller pin has paid itself many times over, and 4 of them are even a bigger deal.

MacTuxLin
11-07-2011, 12:04 AM
Also SPIN will be more than 8X faster so a software implementation will be possible.

Will Spin be faster or GCC?

Heater.
11-07-2011, 08:44 AM
GCC or Catalina or ICC would be faster than Spin.
The former are compiled to native PASM instructions run via LMM or loaded directly into COG. Spin is compiled to byte codes which are then interpreted at run time which will alway be much slower (unless someone is up for creating a Spin to native compiler).
Spin will still have advantages as the byte code executables will alway be smaller than native code so more functionality can be acheived in Spin if the slower speed is acceptable.

Cluso99
11-07-2011, 10:04 AM
spin will be at least 8x faster on propII. Extra speed will also be gained because the hub acesses occur 2x faster and the clut can be used for stack.

Cluso99
11-07-2011, 10:33 AM
4 pins were required for reset, boe, xo and xi. If you look at the pinout this will become clear. It in the instruction document.

MacTuxLin
11-07-2011, 01:30 PM
Spin will still have advantages as the byte code executables will alway be smaller than native code so more functionality can be acheived in Spin if the slower speed is acceptable.

Thanks. Good to know.

davidsaunders
11-12-2011, 05:45 PM
Wow, I have missed out on a lot of info. Do to my time line and the need to bitbang raw video at 120MHz with 16bpp it apears that I will have to use an ARM for the first generation of the MuAmi. I look forward to the Prop2.

hinv
11-12-2011, 08:19 PM
cluso: so you are saying that because of the limitations of the package they couldn't bring out the last 4 pins of port C?
I hope they are available for use internally because they would be useful for control lines for a 32bit internal bus(port D) without encoumbering any of the physical pins.
Having a 32bit bus would be especially handy when a cog wants a transfer from another that is controlling an extrnal SDRAM when lower latency is required than the hub can give.

Cluso99
11-12-2011, 11:07 PM
I would think for sure there is no pin silicon - meaning all the pad circuitry. However, I don't know if the I/O has been done in silicon the same as for Port D. As you say, this could be extremely useful.

HShanko
11-12-2011, 11:21 PM
Aren't we spoiled? There's never enough pins, never enough RAM, never enough cogs!

I've been re-reading the preliminary Feature List for the Prop 2. That will be a bit of a new learning curve for us. A big step up from Prop 1, for sure. Boy, aren't we going to be spoiled with all its features? Can't wait to hear what all some will come up with for the 'new silicon'. Guess 'Santa' won't be bringing any Prop 2 presents this year though.

The more I read, I can imagine there is going to be quite a chore to get the Prop 2 user manual gererated and well explained. Has there ever been any comment on a Prop 2 QuickStart type of board by Parallax?

4x5n
11-12-2011, 11:29 PM
Aren't we spoiled? There's never enough pins, never enough RAM, never enough cogs!

I've been re-reading the preliminary Feature List for the Prop 2. That will be a bit of a new learning curve for us. A big step up from Prop 1, for sure. Boy, aren't we going to be spoiled with all its features? Can't wait to hear what all some will come up with for the 'new silicon'. Guess 'Santa' won't be bringing any Prop 2 presents this year though.

The more I read, I can imagine there is going to be quite a chore to get the Prop 2 user manual gererated and well explained. Has there ever been any comment on a Prop 2 QuickStart type of board by Parallax?

I'm hoping for something like the proto board. I hope that it's available soon. I've got a couple of projects that aren't going well because of the limited number of IO pins and hub memory on the prop I.

Cluso99
11-13-2011, 01:08 AM
There will be a number of different prototype boards available both from Parallax and the community. This has been answered many times before. You can bet they will be available at the launch of the chip - or within a few days - because we have sufficient info to build these boards in advance.

BTW Don't anyone think for one minute that the Prop II will replace the existing Prop 1. It will only fuel more interest in Prop 1 as well. We haven't exhausted use of the features of Prop 1 yet, and so the Prop 1 will still have it's own marketplace. Prop II just opens up many new uses that we just cannot do with Prop 1, or are a chore with Prop 1.

Keith Young
11-13-2011, 09:03 PM
I noticed many people mentioning putting money forward to help with tooling. Is there an official place to sign up? You can count me in for at least $100 as long as I can get a Prop II and a small development board for example, even if I have to wait a year or more to physically get what I paid for.

Have you guys considered selling stock if you aren't already (doesn't seem you do)? I'd love to invest even if it was a measly $1000 bucks I could offer.

I doubt I'm the only one here that's excited about the Prop II and is willing to back it, 40nm or no 40nm.

Cluso99
11-13-2011, 11:51 PM
roughwood: Much of the mention of putting in money was in jest. The fantasy of having a finer geometry like 40nm or whatever, would only delay the Prop II, and we don't really want that - even if the $3M or so was donated without strings.

In reality, it would be just another thing requiring Parallax administration and they are busy enough. Our little amounts would do nothing really to help. And they certainly would not want to lose control of their destiny (and I would not want that either).