Serial out with a 1.5mhz pixel clock pinout using vga mode

[tonyp12]

You are not forced to use PLL internal (video mode) and regular PLL single-ended will work with VGA.

I only have a single channel DSO nano so I can not see both pins.
Q: Is the colors shifted out on falling or rising edge of a PLL clock?

I need the data to be valid for around 8ns before the rising edge of the pixel clock.
So if data and pixel clock are in sync I need to delay pixel clock a little.

Q: A RC delay using 95.3 Ohms and 63 pF would be 12ns, should work?
input threshold min is 0.7 of DVdd (probably not Schmitt triggered)

Other ways would be using 4color mode and implement the pixel clock every other pixel.
or a VSCL with a PixelClocks=2 and using some type of flip/flop to div2 the external clock so It rises in the middle of valid data.


For 48khz 16bit*2 digital audio I need a pixel clock of 1.536mhz

Q: What FRQA should I use with a pll-div of 64
With a 4-8mhz recommended pll input, a 6mhz nco *16pll /64 would be 1.5mhz

[Phil Pilgrim (PhiPi)]

I don't know the answer to the clock phase question offhand, but you can make the determination yourself with a single-channel scope. Just connect the two outputs together via a pair of 1K resistors and observe the waveform at their common (summing) junction.

BTW, if the phase of the clock is different from what you want, just set up for the %00011 (differential PLL) clock mode, and use the inverted clock output instead.

-Phil

[tonyp12]

>(differential PLL) clock mode
Would I be wasting a pin? or can I set A-Pin to pin33+ and it will be ignored?

[Rayman]

I use this mode for a lot of different things such as output to LCDs.
I just set it to a pin I'm not using and use DIRA to make sure it doesn't actually affect the pin...

[kuroneko]

I only have a single channel DSO nano so I can not see both pins.
Q: Is the colors shifted out on falling or rising edge of a PLL clock?
Falling edge. That said, you can observe this by simply looking at it from another cog.


Would I be wasting a pin? or can I set A-Pin to pin33+ and it will be ignored?
Don't setup dira for this pin. Setting 32+ has the same effect as doing so with shift and rotate insns.

[Cluso99]

tonyp12: Unfortunately, the prop does not implement PORTB at all. So you cannot specify them.

[kuroneko]

For 48khz 16bit*2 digital audio I need a pixel clock of 1.536mhz

Q: What FRQA should I use with a pll-div of 64
With a 4-8mhz recommended pll input, a 6mhz nco *16pll /64 would be 1.5mhz
@80MHz I'd use $13A92A30. This gives you a feeder NCO frequency of 6.14399MHz and subsequently a 1.5359999984MHz PLL clock. Close enough I'd say.

Update: Using $13A92A31 would give you 1.5360000031MHz. Take your pick.

[Phil Pilgrim (PhiPi)]

tonyp12,

Just to clarify, the "OUTB" pin in the setup for the differential PLL clock mode has nothing to do with PORTB. As long as you don't set its DIRA bit, you can set the unused clock output to any pin not being used by the cog as an output, including any pin that's used by the cog for input only or any pin used by other cogs for input or output.

-Phil