View Full Version : Is this why prop II is waiting in the wings ?
07-03-2009, 02:25 PM
Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) announced the foundry segment’s first functional 65-nanometer (nm) multi-time programmable (MTP) non-volatile memory (NVM) process technology. The technology incorporates process-qualified MTP IP blocks jointly developed with Virage Logic. The new technology is the first 2.5 volt MTP process, breaking the heretofore 3.3 volt baseline barrier. It eliminates the need for an external EEPROM currently in many systems applications, thereby reducing power, area and costs while increasing data security.
check out the press release
Phil Pilgrim (PhiPi)
07-03-2009, 02:54 PM
No, it's got nothing to do with the Prop II. If memory serves me correctly, the Prop II will use a 1.8V process. It will include no internal non-volatile memory, except for masked ROM.
07-03-2009, 03:10 PM
And I think the Propeller process is quite a bit north of 65nm....
07-04-2009, 01:32 AM
It has nothing to do with TSMC's 65nm process. ... until the multi-time programmable (MTP) non-volatile memory process matures, the IP will be very expensive.
To put the processes in perspective...
Prop I - 350nm process
Prop II - 180nm process .... roughly 1/4th the size of Prop I
65nm would nearly be 1/8th the size of a Prop II
...smaller is not always better, depending on what the chip is doing. At smaller processes you have much more gate leakage that must be dealt with. Moore's law does still apply, but getting this small, some of the physical properties that are well understood at the higher processes start to make a shift where quantum properties become·more dominant.
Beau Schwabe (mailto:email@example.com)
IC Layout Engineer
07-06-2009, 10:09 AM
I believe the prop II chip uses a .18 micron process. In contrast he prop I chip is 3.5 micron.
07-06-2009, 10:24 AM
0.18 micron is 180nm (to be used for Prop II)
0.35 micron is 350nm (currently in use for Prop II)
See Beau's message
FWIW, another well-known family of parallel processing chips uses the TSMC 90nm process, with the 65nm process being used for the new low-cost single core device.
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Post Edited (Leon) : 7/6/2009 6:38:38 AM GMT
07-07-2009, 10:29 AM
As far as complexity goes, how many transistors do the Prop I & II chip's have ?
07-08-2009, 12:41 AM
> As far as complexity goes, how many transistors do the Prop I & II chip's have ?
Less than 1/4 of Propeller III (code name "Deltic engine").
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