jazzed
04-05-2009, 07:36 AM
Hello hardware guys:
I've given some thought to a·16 bit parallel bus external memory XMM Propeller board and am looking for someone
who might take up the challenge. The memory could be used for video buffer or LMM code storage.
Here's the idea. Produce a PCB with Propeller (or two), optional basic IO connectors·like TV (VGA would need too
many pins), mouse, keyboard, audio jack, SD card connector, spin studio header(s), and up to 2MB of 16 bit wide
SRAM (4 512Kx8) or Flash.
Why does 16 bits make sense? Application and speed.
Two main applications are video buffer and LMM code. Video attributes are at least 16 bits wide. LMM instruction
and offset (text) fetch is always 32 bits wide in the ICC kernel and have no need to be anything but long for
instructions or program constants. This means that byte wide access will never happen for these applications.
Speed can come because of·two factors. The first is obvious in that 16 bits can be transfered at once. The second
is a little more subtle and takes patience. I've found that fetching a long or 32 bits using a byte-wide non-latched
address and data path takes at least 17 instructions (someone might do better) for 3.3V 50ns SRAM (20 instructions
for 5V SRAM because of series RC delay).· Fetching 32 bits using a full address/data latch design that would allow
32MB of memory would take at least 15 instructions. Fetching 32 bits using a partial address/data latch design with
up to 2MB memory could take as few as 10 instructions. So an almost·2x read32 XMM fetch·improvement with
16 bit over 8 bit access is possible.
'Initialize XMM kernel fetch for read with SIO (0xc0000000),
'WE* (0x20000000) pulled up, and data (0x0000ffff) as inputs.
'Initialize addrs (0x0fff0000) and ALE (0x10000000) as outputs.
'//call with word-wide address (0x000fffff) in outa reg
read32:
1 shl outa, #8 '// 0x0fffff00 ... upper 12 addr bits ready
2 or outa, ALE '// 0x1fffff00 ... latch upper addr bits
3 shl outa, #8 '// 0xffff0000 ... lower 8 addr bits on bus for read
4 mov tmp2, ina '// get even 16 bit word
5 add outa, K10000 '// odd address
6 shl temp, #16 '// make room for odd word and wait for bus
7 mov tmp2, ina '// get odd 16 bit word
8 or temp, tmp2 '// compose word
9 ror temp, #16 '// swap words to right place
10 ret
In this case there are 4 pins left open on the primary XMM·Propeller that can be used for program load and boot from
SD card, SD ethernet, or whatever purpose including TV display.
Of course the primary could load the XMM from a secondary Propeller attached device. The second propeller could be
connected for communications (using any propeller·pins but most likely 12 pins P16-27) if the LMM interpreter cog can
be stalled for the transaction(s) and atomically send messages·between the primary Propeller's XMM bus accesses.
Using inter-propeller messaging IPM :), many devices can be connected to 16 pins the secondary Propeller.
I will post a block diagram if necessary to more clearly communicate the connection requirements. Attached is an Eagle
schematic that shows most of the interconnects if you can see it for a 1MB SRAM XMM. Some notes describe work TBD
on the schematic.
Any takers?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
--Steve
Propalyzer: Propeller PC Logic Analyzer (http://www.brouhaha.com/~sdenson/Propalyzer)
http://forums.parallax.com/showthread.php?p=788230 (http://forums.parallax.com/showthread.php?p=788230)
I've given some thought to a·16 bit parallel bus external memory XMM Propeller board and am looking for someone
who might take up the challenge. The memory could be used for video buffer or LMM code storage.
Here's the idea. Produce a PCB with Propeller (or two), optional basic IO connectors·like TV (VGA would need too
many pins), mouse, keyboard, audio jack, SD card connector, spin studio header(s), and up to 2MB of 16 bit wide
SRAM (4 512Kx8) or Flash.
Why does 16 bits make sense? Application and speed.
Two main applications are video buffer and LMM code. Video attributes are at least 16 bits wide. LMM instruction
and offset (text) fetch is always 32 bits wide in the ICC kernel and have no need to be anything but long for
instructions or program constants. This means that byte wide access will never happen for these applications.
Speed can come because of·two factors. The first is obvious in that 16 bits can be transfered at once. The second
is a little more subtle and takes patience. I've found that fetching a long or 32 bits using a byte-wide non-latched
address and data path takes at least 17 instructions (someone might do better) for 3.3V 50ns SRAM (20 instructions
for 5V SRAM because of series RC delay).· Fetching 32 bits using a full address/data latch design that would allow
32MB of memory would take at least 15 instructions. Fetching 32 bits using a partial address/data latch design with
up to 2MB memory could take as few as 10 instructions. So an almost·2x read32 XMM fetch·improvement with
16 bit over 8 bit access is possible.
'Initialize XMM kernel fetch for read with SIO (0xc0000000),
'WE* (0x20000000) pulled up, and data (0x0000ffff) as inputs.
'Initialize addrs (0x0fff0000) and ALE (0x10000000) as outputs.
'//call with word-wide address (0x000fffff) in outa reg
read32:
1 shl outa, #8 '// 0x0fffff00 ... upper 12 addr bits ready
2 or outa, ALE '// 0x1fffff00 ... latch upper addr bits
3 shl outa, #8 '// 0xffff0000 ... lower 8 addr bits on bus for read
4 mov tmp2, ina '// get even 16 bit word
5 add outa, K10000 '// odd address
6 shl temp, #16 '// make room for odd word and wait for bus
7 mov tmp2, ina '// get odd 16 bit word
8 or temp, tmp2 '// compose word
9 ror temp, #16 '// swap words to right place
10 ret
In this case there are 4 pins left open on the primary XMM·Propeller that can be used for program load and boot from
SD card, SD ethernet, or whatever purpose including TV display.
Of course the primary could load the XMM from a secondary Propeller attached device. The second propeller could be
connected for communications (using any propeller·pins but most likely 12 pins P16-27) if the LMM interpreter cog can
be stalled for the transaction(s) and atomically send messages·between the primary Propeller's XMM bus accesses.
Using inter-propeller messaging IPM :), many devices can be connected to 16 pins the secondary Propeller.
I will post a block diagram if necessary to more clearly communicate the connection requirements. Attached is an Eagle
schematic that shows most of the interconnects if you can see it for a 1MB SRAM XMM. Some notes describe work TBD
on the schematic.
Any takers?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
--Steve
Propalyzer: Propeller PC Logic Analyzer (http://www.brouhaha.com/~sdenson/Propalyzer)
http://forums.parallax.com/showthread.php?p=788230 (http://forums.parallax.com/showthread.php?p=788230)