View Full Version : HELP, Chip, re: WAITPEQ

04-01-2009, 03:47 AM
I may need Chip Gracey's comments on this. For some reason the WAITPEQ instruction doesn't work as expected. Probably some silly, simple reason(s).

The WAITPEQ seems to be a perfect instruction for my application (comparing 17 bit INA looking for a match). I'm planning to use COGSTOP and COGINIT to stop the 'lockup' of WAITPEQ and restart this cog for when a match doesn't occur. Any comments on this plan?

The NOPs are used to stretch the output pulse width during debug viewing. The XOR (at ':loop') is just to toggle the pulse line during debug and the WRLONG and WAITPNE are commented out at this time. Here's my code for this cog:

'**************************************** MUST BE LAST COG, IF USE PASD
' BAbus comparator - SBPt = breakpoint value, bit 16 set, upper 15 bits Zeroed; pg.1
'entry '----- Debugger Kernel add this at Entry (Addr 0) --------
' long $34FC1202,$6CE81201,$83C120B,$8BC0E0A,$E87C0E03,$8 BC0E0A
' long $EC7C0E05,$A0BC1207,$5C7C0003,$5C7C0003,$7FFC,$7FF 8
' --------------------------------------------------------------

BAbusRd or DIRA,INTR1msk ' set /INTR pin to output
or OUTA,INTR1msk ' set to HI level
wrlong zed0,PAR ' ensure PAR clearon entry
:loop xor OUTA,INTR1msk ' added for visual view in VP
test INTRpin,INA wz,wc ' ck for Prop#1 'interrupt' (A27)
if_nz jmp #:doINTR ' if LO, generate interrupt to Pod
rdlong BAcomp,PAR wz ' get/test if valid BP value
if_z jmp #:loop ' wasn't, continue to loop

' wrlong zed0,PAR ' clear PAR for single BP event
' waitpne BM1mask,BM1mask ' wait for BM1 at LO level
andn OUTA,INTR1msk ' VP neg sync (LO) (A19)
nop ' 8 x 50 nsec/ = 400 nsec LO
or OUTA,INTR1msk
waitpeq BAcomp,BAbusMask ' wait for breakpoint compare
:doINTR andn OUTA,INTR1msk ' output negative pulse
nop ' stretch for viewing, because ViewPort cannot display
nop ' first several hundred nseconds of events after trigger
nop ' 10 x 50 nsec/ = 500 nsec LO
or OUTA,INTR1msk ' return to HI level
:hang0 test INTRpin,INA wz ' wait until A27/pin36 goes LO (~ 7 - 8 microsec)
if_nz jmp #:hang0
jmp #:loop ' return to ck for Prop#1 interrupts
' Above instructions take 4 system clocks, except RDLONG, WRLONG (7..22) and WAITPEQ (5+)
' Initialized data for 'BAbusRd'
BM1mask long |<16 ' mask for only BM1 pin (A16) event $0001_0000
BAbusMask long $0001_FFFF ' BM1 + 16 Z80 addr bits mask
'INTR1msk long |<21 ' mask for /INTR on A21/pin 26
INTR1msk long |<19 ' bit 19, pin 24; used to debug BAbusRd ???
INTRpin long |<27 ' interrupt from Prop#1 on A27/pin 36
zed0 long 0 ' to clear PAR
' Unitialized data for 'BAbusRd'
BAcomp RES 1 ' holds 'breakpoint' value from SBt; compare w/BAbus value
FIT 496

In the past I've gotten suggestions of using other code, which takes more time than WAITPEQ, as I need minimum delay between comparison and generating an output pulse.

1. The manual says INA if C = 0...(the P8X32A is an exception to this rule; it always tests INA)/ Does this imply C is not really involved or need be set to C = 0 for the P8X32A?

2. Can the State register be changed and used by WAITPEQ after the instruction is run, but no INA match occurs?

Thanks for any help on this matter.

Harley Shanko

04-01-2009, 03:56 AM
Be sure that you are toggling PA16 (so bit 17). It should work.

04-01-2009, 03:58 AM
Hi Harley!
Waitpeq is very useful. It lets you pause the cog's execution until INA ANDed with the specified mask equals the specified state. For the current propeller, the C flag doesn't do anything. The state and mask data is read in during the first part of the cycle- you can't change them after the fact. The only thing you can do is stop the cog and restart it. This is what ViewPort does when you change triggers inside the logic state analyzer.

Phil Pilgrim (PhiPi)
04-01-2009, 04:44 AM
If you must use COGINIT, don't do a COGSTOP first. Not only is it unnecessary but, between your COGSTOP and COGINIT, another cog may do a COGNEW and grab it.

The (i.e. my) rule is this: unless the cog is already running and you just want to restart it, use COGNEW, not COGINIT.