View Full Version : Best practice Power/Ground on Propeller Chip

Jeff Martin
03-19-2009, 05:24 AM

During yesterday's webinar with Chip, the topic came up that our belief as to what is causing the rare PLL burn-out failures has to do with unwanted electrical potentials created by a custom Propeller board's·layout connections, or lack thereof.·

We have not been able to prove this theory, but we have also not witnessed this failure on the Propeller Demo board.· So we thought we'd share the attached images of the layout for the Propeller Demo Board as a "best practice" reference for future Propeller board/circuit designs.


--Jeff Martin

· Sr. Software Engineer
· Parallax, Inc.

Post Edited (Jeff Martin (Parallax)) : 3/19/2009 6:46:15 PM GMT

Fred Hawkins
03-19-2009, 08:05 AM
Jeff, these look like they are intended for the LQFP chip. Datasheet v1.0 doesn't show a center pad for the LQFP. So may I assume this center block is just a thermal pad? Also, am I correct that this best practice holds the center pad at 3.3v (Vdd)?

Finally, on the QFN chip, which does have a center pad, won't there be another solution? The ground vias under its center pad don't seem correct.

Post Edited (Fred Hawkins) : 3/19/2009 8:52:32 AM GMT

Timothy D. Swieter
03-19-2009, 08:47 AM
The images shown are the traces/pads/copper areas for the Propeller Demo Board which uses the QFP part. The QFP part doesn't have a pad, in the middle of the IC, you are right. The copper pour/area is probably just a helper for layout purposes - a very large trace or area. Not necessarily a thermal pad, it doesn't connect to anything for heat dissipation. If there was an image of the soldermask it would probably be more evident.

In the design that I have done I have done something similar, but I made the center pour area be VSS (GND) and the smaller traces be VDD. But of course this is a nice looking layout because the GND plane/copper pour on the bottom layer. Interesting how this is different, inspiring some too.

What does the Propeller Protoboard layout look like compared to this?

Timothy D. Swieter, E.I.
www.brilldea.com (http://www.brilldea.com) - Prop Blade, LED Painter, RGB LEDs, 3.0" LCD Composite video display, eProto for SunSPOT
www.tdswieter.com (http://www.tdswieter.com)

Phil Pilgrim (PhiPi)
03-19-2009, 01:34 PM
Some examples I've read about of the "PLL" failure seem to indicate that it's not the PLL itself that fails but the metalization providing power to parts of the chip. Here's my reasoning: some have reported "PLL" failures using PLLx16, but that everything works fine using PLLx4, for example. But if the PLL itself had really failed, none of the PLL modes would work, since they're all divided down from PLLx16. So what does that leave? Well, the only other difference among the PLL modes, other than clock speed, is power consumption. If the device will run so long as it requires little power (i.e. low clock speed), but fails at higher power levels, this would seem to indicate a compromised power distribution system within the chip. Combine this with reports that these failures often occur after a pin or pins have been stressed, due either to a short or to a too-high voltage being applied, and the power distribution idea makes even more sense.

But I'm not an IC design expert, so this is just speculation on my part.


03-19-2009, 01:52 PM
Hi Jeff Martin (Parallax).

This is my pictures for.
Reconstructed ProtoBoard for stablity with 14 MHz crystal

Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


Post Edited (Sapieha) : 3/19/2009 6:57:21 AM GMT

Timothy D. Swieter
03-19-2009, 01:58 PM
Phil -

I think what Chip said in the webinar (soon it will be on video and we can confirm) is that he thought is was something that was stressed and broken in the interface logic to the PLL. Chip said that he didn't think the PLL itself broke, but the interface logic to it.

Your reasoning on power distribution makes sense too. It would be neat to dissect a chip that has had this happen and see what is found.

Timothy D. Swieter, E.I.
www.brilldea.com (http://www.brilldea.com) - Prop Blade, LED Painter, RGB LEDs, 3.0" LCD Composite video display, eProto for SunSPOT
www.tdswieter.com (http://www.tdswieter.com)

Dennis Ferron
03-21-2009, 12:05 AM
I had a PLL failure on the PropStick kit. (Not to be confused with the PropStick USB; the kit I'm referring to used a DIP-packaged Propeller and had a 9-pin serial port, not USB. Last I checked, the product was discontinued.) Anyhow nice kit, but if I set any PLL mode at all, no matter what the multiplier, the Propeller would stop responding. Worked fine if it was running from internal RC clock. I sent the chip back and Parallax sent me a new one, and the kit has been working fine ever since. I don't know what the power distribution layout was on the PropStick kit board, but it would seem to correlate with the idea that a different power layout has something to do with it, because it was a 3rd party design. The fact that I couldn't set any PLL mode (if I recall that correctly) doesn't match up, but maybe it is just that the failure shows up differently if it happens at different places?

I was a little harsh on Nick McClick when I warned him that he better ground both ground pins in his Propeller reference board kit; I didn't know about this problem, but recommended it just from general principle. Looks like I wasn't crying wolf after all!

Phil Pilgrim (PhiPi)
03-21-2009, 12:38 AM

The DIP has only two Vdd/Vss pairs, contrasted with four for the SMT packages. In the PropStick Kit (which I designed), Vss is a groundplane on the component side; Vdd, a 50-mil trace on the solder side. There is one 10uF filter cap (tantalum) and two 0.1uF bypass caps: one for the Prop/EEPROM, and one for the MAX3232. Had there been room, I'd have added another for the Prop. Attached is the board layout.

In my current work with the SMT part, I use two 1uF ceramic bypass caps on opposite sides of the chip, and both power and ground planes underneath the chip, similar to the layout Jeff posted.


Fred Hawkins
04-02-2009, 10:41 PM
Kicking this thread back to the top of the heap to force a reply from Parallax's guys (third time asking may be a charm) on these questions:

What is the corresponding best practice for the QFN prop chip?

Can I arbitrarily use the center pad as either ground or vdd?

Fred Hawkins
04-25-2009, 04:40 PM
Worth noting: the latest Propeller Datasheet (v1.1) adds the stencil pattern for the qfn chip. On page 36.

Not quite the answer I was looking for, but it'll do for now.