View Full Version : Propeller logic threshold

Larry C.
01-08-2009, 08:30 AM
I'm in the process of evaluating the sigma-delta A to D converter circuit described in the App Note AN-001 for a project I have in mind. The zero offset depends on the ratio of the input resistor and the feedback resistor, and the size of the offset can be fairly large. For instance, with the converter resolution set to 12 bits, or 4095 counts full scale, and with R(feedback) = 100 kohms and R input = 150 kohms, the ADC output is over 1200 counts with zero input volts. That's OK, I can just subtract it out in software, but it cuts down the total range. I'd like to avoid this. The lower the value of R input, the lower the offset, which is pretty much gone when R input is reduced to about 82 kohms. So now I have nearly the whole 4000-plus count range to use.

I'm guessing the explanation is that the above resistor values form a voltage divider whose output just matches the logic threshold of the Propeller input pin when the input is at zero volts.

That brings up the question: Does anybody know if the logic threshold voltage on the Propeller inputs is a controlled parameter? OR does it vary all over the map?

I'd really like to maximize the useable A to D converter range, so I'd like to know if the threshold is consistent from chip to chip, or even from one input pin to another on the same chip.

Thanks for any help,

Larry C.

01-08-2009, 08:43 AM
good question... I'm guessing it is a batch issue.


page 4

input high 1/2 VDD ... to VDD // doesn't discuss variance


Peter Jakacki
01-08-2009, 08:45 AM
The logic threshold Vih and Vil are guaranteed within certain limits but the A/D rides the no-mans land and relies on the CMOS gate design which seems to avoid translating that to an analog voltage. This is probably because of the output buffer MOSFETs of the input gate plus the succeeding logic as well flipping to a high or low, so it seems to translate this precariously positioned input to a valid or low. This is what a comparator is designed to do as it uses a high-slew rate high-gain amplifier to achieve this plus a voltage reference, the Propeller has none of this so this, there are no guarantees. Do not expect too much.


Larry C.
01-08-2009, 11:40 PM
OK, that's sorta what I suspected.

Looks like I'll have to add a separate precision comparator if I want a more consistent response. Oh, well....

I'm working on a project for hobbyists to build and I am trying to keep the chip count and complexity
to a minimum. With the exception of this little design glitch, the Propeller is ideal for what I want.

Nice chip!

01-09-2009, 04:28 AM
The Propeller's input circuits are just minimum-sized inverters that are PMOS:NMOS ratio'd to yield a ~VDD/2 threshold from·typical wafer fabrication runs. So, they are not accurate comparators, but very simple two-transistor,·high-speed, low-power logic sensors. Real VDD/2 comparison would require some quiescent current expenditure.

The next Propeller will have very fast VDD/2 sensing for internal analog-to-digital conversion. You'll have to turn it on, though, as it takes extra power.


Chip Gracey
Parallax, Inc.

Larry C.
01-09-2009, 08:17 AM
Good! I can think of several projects that could make good use of that.

How fast do you anticipate the "very fast VDD/2 sensing" will be?? What would be the power hit when it's enabled?

Larry C.

01-09-2009, 08:18 AM
Remember that a simple RC system for an ADC, is going to have limitations.
The problem is the LSB info leaks due to the timeconstant effects

If you want to push to 12 bits of precision/linearity, then an external integrator
will be better than a comparitor, as that gives far more
accurate charge accumulation.

Hopefully, the next propellor allows the choice of the buried RC, or external
integrator for better presision ?

Larry C.
01-10-2009, 08:20 AM

Good point. I didn't think of that.

So, if my number crunching is correct, in order to maintain a droop of less than one LSB, worst case scenario, at 12 bits resolution,
I'm gonna need a RC time constant about 4000 times as long as the sample period.

At 80 MHz clock, the sample period is about 50 microsec (according to AN-001), and 4000 * 50 microsec = 200 millisec or more.

Hmmm. This will slow things down. Fortunately, my application deals with slowly-changing inputs (near dc) so I could probably
get away with this approach. But for anything faster, no way.

Thanks for the insight.

01-10-2009, 11:08 AM
You could build both, and compare them ?

ie a RC with LSB-rated cap, and an integrator with your choice of threshold on another channel.

On most chips, the pins track quite well, so if you use the simpler RC,
you could add some useful zero compensation (temperature/process)
with a second channel, that simply measures the Pin Threshold.