PDA

View Full Version : Video Input; Image Sampling



LustInBlack
01-14-2008, 03:06 AM
Hello,


I don't know much yet about the Propeller, I've seen the datasheet and I know the chip is supposed to achieve
about 160MIPS with the 8 cogs running..


I want to sample video from a VGA connector and fill external RAM or display directly to a TFT LCD with a digital interface..

Since the chip is supposed to run at 160 MIPS, I expect it to be able to sample easily a 25mhz signal..
The only thing I will need externally, is a ADC converter for the R,G and B signals..

Since I don't know much about the chip, is it possible to take 3 cogs and use them in cascade to decode
the three component of the video and use 3 other cogs to output those RGB signals digitally on another
digital port (I will use 3 latches on 8 pins for the digital video components)!? ..


Basicly, I want the chip to act as an interface between a ADC and a Digital LCD or RAM ..

The only thing I am not familiar with, is the way cogs keep in synch ...

Btw, what is the maximum achieveable square-wave frequency using assembly code!?
8 cogs running at full speed in tight loops transition from 1 to 0 on 1 pin ....



Thanks for the help!

deSilva
01-14-2008, 03:32 AM
These are often posted questioned. I am sure others will lead you to the threads and discussions about frame grabbing, external RAMs, and synchronized COGs...

To your last question: It's 1/2 of the system clock (80/2 MHz), without using the PLL, which can boost square waves by a factor of 16 (though not this 40 MHz).
This will be done by one of the 8 independent timers/counters.
The tightest loop is this:



:loop
XOR OUTA, thePinMask
DJNZ cycles, #:loop


which takes 100 ns -> 5 MHz
By an external XOR gate you can combine this by phase locked output of one or three of the other COGs to double or quadruple it.

-----
Edit: I just remember a demonstration where I doubled it http://forums.parallax.com/images/smilies/smile.gif


MOV DIRA,#1
DJNZ OUTA, #$


But this (10MHz) works only at I/O pin 0

Post Edited (deSilva) : 1/13/2008 7:55:16 PM GMT

LustInBlack
01-14-2008, 04:09 AM
Ok, so basicly, it's not possible to output on ports faster than 5 or 10 mhz. ..

In comparison with an ATMEL MCU, is this slower !?

All instructions on an ATMEL MCU (8 bit) is supposed to be done in 1 clock .. I believe @ 20mhz, I should achieve 10mhz on
the ATMEL .. What is the advantage of having 8 cogs then !? ..

I think I don't understand yet the capabilities of the propeller chip ...

EDIT : To be noted, that I don't know if it's possible to output on the same io pin with all cogs, which seem to not be
the case because you mentionned that an external Gate is needed to take the transition from all cogs on each pin..

Post Edited (LustInBlack) : 1/13/2008 8:16:47 PM GMT

deSilva
01-14-2008, 04:31 AM
LustInBlack said...
I think I don't understand yet the capabilities of the propeller chip ...

Very few do...
You asked for examples which can be more easily done by an MSI chip (as 74AHCxx..) They will deliver you 300 MHz for 10 Cents each chip.

Being able to manipulate 32 bits in one instruction CAN release you from many 8 bit burdens.
And the 1 clock per instruction marketing of the AVR chips is - marketing, as the 160 MIPS for the propeller is... Yes, you can construct cases...

Not measured, just as a feeling: I should say an algorithm running in one COG (running @80MHz) is around 8 times faster than the same algorithm running on a 20 MHz ATmega-88.

This will change to the disadvantage of the Propeller when you run algorithms specifically TUNED to 8 bit operations.

On the other hand you get EIGHT processors.

Faster output can be generated by the video-logic (there are eight of them!)
You can output a square wave by



:loop
WAITVID a,b
DJNZ cycles,#:loop


during this 100 ns a maximum of 32 bits can be shifted out (so make it 16 low and 16 high), giving you 160 MHz.

This however will soon be reduced by needed "modulation". The main advantage with the video logic is that it works in parallel with the code computing/reading the data. The latter is the bottleneck, and figures WRT square waves are not really so relevant...

Multiple COGs (mostly 4) have been synchronized and burst rates of 40 MHz have been reported for sending or receiving REAL data .

Post Edited (deSilva) : 1/13/2008 8:40:54 PM GMT

RinksCustoms
01-14-2008, 10:13 AM
I know deSilva has alot more expierience with these systems than i, but from what i know of the counters labs, the 16 counter modules (2 per cog) with the counters video PLL can generate up to a (useful) 128MHz square wave. I know i'm probably misreading the lab though.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
E3 = Thought

http://folding.stanford.edu/ (http://folding.stanford.edu/)ˇ- Donating some CPU/GPU downtime just might lead to a cure for cancer! My team stats. (http://vspx27.stanford.edu/cgi-bin/main.py?qtype=teampage&teamnum=78528)

deSilva
01-14-2008, 04:41 PM
No, you just repeat whats in the datasheet; it says that the PLL should best be used between 4 and 8 MHz, resulting in 128 MHz max. This however is a quite defénsive statement. I said above that you should not use the PLL with 40 MH , that would (not!) result in 640 Mhz http://forums.parallax.com/images/smilies/smile.gif The truth lies somewhere in between and more on the 128 Mhz edge. Note however that a PLL boosted signal is not so easy to control...